Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits Conference Paper uri icon

abstract

  • This paper presents a novel design approach for addressing the pressing problem of noise and signal integrity in highspeed circuits. The approach uses a combination of gatelevel redundancy in form of a shadow circuit, exception handling, and retry to tolerate random and delay faults that are of increasing concern in modern circuits. An empirical evidence of the delay/random fault problem is developed and a scheme to press clocking frequency beyond traditional limit is presented. The results show that approximately 10% improvement in clocking frequency can be achieved with almost negligible performance penalty and 5%-20% area overhead for the benchmark circuits studied. 2007 IEEE.

name of conference

  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

published proceedings

  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

author list (cited authors)

  • Chang, S., & Choi, G.

citation count

  • 1

complete list of authors

  • Chang, Sanghoan||Choi, Gwan

publication date

  • January 2007

publisher