Si-emulation: System verification using simulation and emulation Conference Paper

abstract

• A system-level verification framework is presented that combines the speed of hard-wired (FPGA-based) emulation and the observability of gate-level simulation. A checkpoint approach is developed for 1) periodic capturing of the machine state from an emulation, 2) sampling of the emulation output for error detection, and 3) constructing a piece-wise simulation run, necessary to debug the design in an event of an error detection from the emulation. The checkpoint frequency is optimized to reduce to cost of downloading the state data during a hardware emulation. A sampling of the emulation output also minimizes the network-bandwidth and storage-space requirements associated with instrumenting for error detection.

name of conference

• Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)

authors

• Choi, Gwan

published proceedings

• INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS

author list (cited authors)

• Yang, Z., Min, B. Y., & Choi, G.

citation count

• 5

complete list of authors

• Yang, Z||Min, BY||Choi, G

publication date

• January 2000

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• International Test Conference  Journal

keywords

• 40 Engineering
• 4008 Electrical Engineering

Digital Object Identifier (DOI)

• 10.1109/TEST.2000.894203

International Standard Book Number (ISBN) 10

• 0-7803-6546-1

start page

• 160

end page

• 169

URL

• http://dx.doi.org/10.1109/test.2000.894203