Si-emulation: system verification using simulation and emulation Conference Paper uri icon


  • A system-level verification framework is presented that combines the speed of hard-wired (FPGA-based) emulation and the observability of gate-level simulation. A checkpoint approach is developed for 1) periodic capturing of the machine state from an emulation, 2) sampling of the emulation output for error detection, and 3) constructing a piece-wise simulation run, necessary to debug the design in an event of an error detection from the emulation. The checkpoint frequency is optimized to reduce to cost of downloading the state data during a hardware emulation. A sampling of the emulation output also minimizes the network-bandwidth and storage-space requirements associated with instrumenting for error detection.

name of conference

  • International Test Conference 2000

published proceedings

  • Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)

author list (cited authors)

  • Zan Yang, .., Byeong Min, .., & Gwan Choi.

citation count

  • 5

publication date

  • January 2000