Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router Conference Paper uri icon


  • Networks-on-Chips are gaining in popularity as replacement for shared medium interconnects in chip-multiprocessors (CMPs) and multiprocessor systems-on-chips (MPSoCs), and their performance becoming essential to system performance. We propose a dual-path router architecture that efficiently exploits path diversity to attain low latency and high throughput without significant hardware overhead. By 1) doubling the number of injection and ejection ports, 2) splitting packets into two halves, 3) recomposing routing policy to support path diversity, and 4) provisioning the network hardware design, we can significantly improve network resource utilization to achieve much higher throughput and lower latencies. Results show that the proposed dual-path router improves saturation bandwidth by 29% on uniform random synthetic traffic, while achieving a reduction in average packet latency of 31% and 17% for uniform random synthetic traffic and video benchmarks respectively. 2012 IEEE.

name of conference

  • 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012

published proceedings

  • 2012 IEEE International Symposium on Circuits and Systems

author list (cited authors)

  • Yang, Y. S., Deshpande, H., Choi, G., & Gratz, P.

citation count

  • 3

complete list of authors

  • Yang, Yoon Seok||Deshpande, Hrishikesh||Choi, Gwan||Gratz, Paul

publication date

  • May 2012