HR job title
- Professor
- Contact Info
- 1 979 488 4551
- Websites
Gratz, Paul Professor
Positions
- Professor, Electrical and Computer Engineering, College of Engineering
- Associate Professor, Electrical and Computer Engineering, College of Engineering
I lead the CAMSIN research group, where our computer architecture research focuses on power, reliability and performance of the future chip-multiprocessor (CMP) and multiprocessor system-on-chip (MPSoC) designs.
Research Areas
- Overview
- Publications
- Research
- Teaching
- Works By Students
- Background
- Contact
- Other
- View All
Overview
Publications
selected publications
-
academic article
-
Chacon, G. A., Williams, C., Knechtel, J., Sinanoglu, O., Gratz, P. V., & Soteriou, V.
(2024).
Coherence Attacks and Countermeasures in Interposer-Based Chiplet Systems. ACM Transactions on Architecture and Code Optimization (TACO).
21(2), 1-25.
-
Qin, M., Zheng, Q., Lee, J., Settlemyer, B., Wen, F., Reddy, N., & Gratz, P.
(2023).
KVRangeDB: RangeQueries for a Hash-based Key-Value Device. ACM Transactions on Storage.
19(3), 1-21.
-
Jimenez, D., Teran, E., & Gratz, P.
(2023).
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching. IEEE Computer Architecture Letters.
22(1), 17-20.
-
Tirumalasetty, C., Chou, C. C., Reddy, N., Gratz, P., & Abouelwafa, A.
(2022).
Reducing Minor Page Fault Overheads through Enhanced Page Walker. ACM Transactions on Architecture and Code Optimization (TACO).
19(4), 1-26.
-
Wang, P., Wen, F., Gratz, P. V., & Sprintson, A.
(2022).
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework. ACM Transactions on Architecture and Code Optimization (TACO).
19(3), 1-20.
-
Chacon, G. A., Williams, C., Knechtel, J., Sinanoglu, O., & Gratz, P. V.
(2022).
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. IEEE Computer Architecture Letters.
21(2), 133-136.
-
Wen, F., Qin, M., Gratz, P., & Reddy, N.
(2022).
Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems. ACM Transactions on Embedded Computing Systems.
21(1), 1-18.
-
Wen, F., Qin, M., Gratz, P. V., & Reddy, A.
(2020).
Hardware Memory Management for Future Mobile Hybrid Memory Systems. 39(11), 3627-3637.
-
Chou, C. C., Jung, J., Reddy, A., Gratz, P. V., & Voigt, D.
(2020).
Virtualize and share non-volatile memories in user space. CCF Transactions on High Performance Computing.
2(1), 16-35.
-
Wang, P., Mchale, L., Gratz, P. V., & Sprintson, A.
(2019).
GenMatcher: A Generic Clustering-Based Arbitrary Matching Framework. ACM Transactions on Architecture and Code Optimization (TACO).
15(4), 1-22.
-
Ramrakhyani, A., Gratz, P. V., & Krishna, T.
(2019).
Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom. IEEE Micro.
39(3), 110-117.
-
AlBarakat, L. M., Gratz, P. V., & Jimenez, D. A.
(2018).
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. IEEE Computer Architecture Letters.
17(2), 175-178.
-
Le Beux, S., Gratz, P. V., & O'Connor, I.
(2018).
Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques. IEEE Transactions on Multi-Scale Computing Systems.
4(2), 97-98.
-
Yang, Y. S., Deshpande, H., Choi, G., & Gratz, P. V.
(2018).
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
37(3), 545-558.
-
Kim, J., Teran, E., Gratz, P. V., Jimenez, D. A., Pugsley, S. H., & Wilkerson, C.
(2017).
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. ACM SIGPLAN NOTICES.
52(4), 737-749.
-
Won, J., Gratz, P. V., Shakkottai, S., & Hu, J.
(2016).
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. ACM Transactions on Design Automation of Electronic Systems.
21(4), 1-25.
-
Ramakrishna, M., Kodati, V. K., Gratz, P. V., & Sprintson, A.
(2016).
GCA:Global Congestion Awareness for Load Balance in Networks-on-Chip. IEEE Transactions on Parallel and Distributed Systems.
27(7), 2022-2035.
-
Kim, H., Boga, S., Vitkovskiy, A., Hadjitheophanous, S., Gratz, P. V., Soteriou, V., & Michael, M. K.
(2015).
Use It or Lose It. ACM Transactions on Design Automation of Electronic Systems.
20(4), 1-26.
-
Li, C., Browning, M., Gratz, P. V., & Palermo, S.
(2014).
LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
33(6), 826-838.
-
Kim, H., Grot, B., Gratz, P. V., & Jimenez, D. A.
(2014).
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. IEEE Transactions on Computers.
63(3), 543-556.
-
Yang, Y. S., Kumar, R., Choi, G., & Gratz, P. V.
(2014).
WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture. ACM Transactions on Design Automation of Electronic Systems.
19(4), 1-22.
-
Fedorov, V. V., Qiu, S., Reddy, A., & Gratz, P. V.
(2013).
ARI: Adaptive LLC-Memory Traffic Management. ACM Transactions on Architecture and Code Optimization (TACO).
10(4), 1-19.
-
Chen, X. i., Xu, Z., Kim, H., Gratz, P., Hu, J., Kishinevsky, M., & Ogras, U.
(2013).
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches. ACM Transactions on Design Automation of Electronic Systems.
18(4), 1-21.
-
Panda, R., Gratz, P. V., & Jimenez, D. A.
(2012).
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. IEEE Computer Architecture Letters.
11(2), 41-44.
-
Jain, T., Ramakrishna, M., Gratz, P. V., Sprintson, A., & Choi, G.
(2011).
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm. 30(11), 1663-1676.
-
Kim, H., & Gratz, P. V.
(2010).
Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect. IEEE Computer Architecture Letters.
9(1), 33-36.
-
Gebhart, M., Maher, B. A., Coons, K. E., Diamond, J., Gratz, P., Marino, M., ... McKinley, K. S.
(2009).
An evaluation of the TRIPS computer system. Computer architecture news.
37(1), 1-12.
-
Gratz, P., Kim, C., Sankaralingam, K., Hanson, H., Shivakumar, P., Keckler, S. W., & Burger, D.
(2007).
On-chip interconnection networks of the trips chip. IEEE Micro.
27(5), 41-50.
-
Burger, D., Keckler, S. W., McKinley, K. S., Dahlin, M., John, L. K., Lin, C., ... Yoder, W.
(2004).
Scaling to the end of silicon with EDGE architectures. Computer.
37(7), 44-55.
-
Chacon, G. A., Williams, C., Knechtel, J., Sinanoglu, O., Gratz, P. V., & Soteriou, V.
(2024).
Coherence Attacks and Countermeasures in Interposer-Based Chiplet Systems. ACM Transactions on Architecture and Code Optimization (TACO).
21(2), 1-25.
-
chapter
-
Li, C., Gratz, P. V., & Palermo, S.
(2015).
Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors. More than Moore Technologies for Next Generation Computer Design.
(pp. 155-186).
Springer Nature.
-
Gratz, P., & Keckler, S.
(2010).
Introduction to Network Architectures. Designing Network On-Chip Architectures in the Nanoscale Era.
(pp. 41-70).
Taylor & Francis.
-
Keckler, S., Burger, D., Sankaralingam, K., Nagarajan, R., McDonald, R., Desikan, R., ... Shi, P.
(2007).
Architecture And Implementation Of The Trips Processor. Unique Chips and Systems.
(pp. 1-40).
Taylor & Francis.
-
Li, C., Gratz, P. V., & Palermo, S.
(2015).
Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors. More than Moore Technologies for Next Generation Computer Design.
(pp. 155-186).
Springer Nature.
-
conference paper
-
Chacon, G., Gober, N., Nathella, K., Gratz, P. V., & Jimenez, D. A.
(2023).
A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end. 61-70.
-
Chacon, G., Garza, E., Jimborean, A., Ros, A., Gratz, P. V., Jimenez, D. A., & Mirbagher-Ajorpaz, S.
(2022).
Composite Instruction Prefetching. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
471-478.
-
AlBarakat, L. M., Gratz, P. V., & Jimenez, D. A.
(2022).
SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
50-58.
-
Vavouliotis, G., Chacon, G., Alvarez, L., Gratz, P. V., Jimenez, D. A., & Casas, M.
(2022).
Page Size Aware Cache Prefetching. Micro -Annual Workshop then Annual International Symposium-.
956-974.
-
Chen, K., Gratz, P., Kim, J., Narayanan, V., & Ogras, U.
(2022).
Panel: The Future of NoCs: Challenges and Opportunities. 1-1.
-
Farrokhbakht, H., Gratz, P. V., Krishna, T., San Miguel, J., & Jerger, N. E.
(2022).
Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing. Proceedings - International Symposium on High-Performance Computer Architecture.
957-970.
-
Wen, F., Qin, M., Gratz, P., & Reddy, N.
(2021).
OpenMem: Hardware/Software Cooperative Management for Mobile Memory System. Design Automation Conference.
109-114.
-
Barboza, E. C., Jacob, S., Ketkar, M., Kishinevsky, M., Gratz, P., & Hu, J.
(2021).
Automatic Microprocessor Performance Bug Detection. Proceedings - International Symposium on High-Performance Computer Architecture.
545-556.
-
Farrokhbakht, H., Kao, H., Hasan, K., Gratz, P. V., Krishna, T., San Miguel, J., & Jerger, N. E.
(2021).
Pitstop: Enabling a Virtual Network Free Network-on-Chip. Proceedings - International Symposium on High-Performance Computer Architecture.
682-695.
-
Radaideh, A. M., & Gratz, P. V.
(2021).
CMRC: Comprehensive Microarchitectural Register Coalescing for GPGPUs. 1803-1808.
-
Wen, F., Qin, M., Gratz, P., & Reddy, N.
(2021).
An FPGA-based Hybrid Memory Emulation System. 190-196.
-
Qin, M., Reddy, A., Gratz, P. V., Pitchumani, R., & Ki, Y. S.
(2021).
KVRAID: High Performance, Write Efficient, Update Friendly Erasure Coding Scheme for KV-SSDs. 1-12.
-
Parasar, M., Jerger, N. E., Gratz, P. V., San Miguel, J., & Krishna, T.
(2021).
SEEC: Stochastic Escape Express Channel. International Conference for High Performance Computing, Networking, Storage and Analysis, SC.
-
Radaideh, A. M., & Gratz, P. V.
(2020).
Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs. Design Automation Conference.
1-6.
-
AlBarakat, L. M., Gratz, P. V., & Jimnez, D. A.
(2020).
SB-Fetch. 1-12.
-
Parasar, M., Farrokhbakht, H., Jerger, N. E., Gratz, P. V., Krishna, T., & San Miguel, J.
(2020).
DRAIN: Deadlock Removal for Arbitrary Irregular Networks. Proceedings - International Symposium on High-Performance Computer Architecture.
447-460.
-
Qin, M., Lee, J. H., Pitchumani, R., Ki, Y. S., Reddy, N., & Gratz, P. V.
(2020).
A Generic FPGA Accelerator for Minimum Storage Regenerating Codes. 271-276.
-
Yaghini, P. M., Michelogiannakis, G., & Gratz, P. V.
(2019).
SpecLock: Speculative Lock Forwarding. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
273-282.
-
Chou, C. C., Chen, Y., Milojicic, D., Reddy, A., & Gratz, P. V.
(2019).
Optimizing Post-Copy Live Migration with System-Level Checkpoint Using Fabric-Attached Memory. 16-24.
-
Parasar, M., Jerger, N. E., Gratz, P. V., San Miguel, J., & Krishna, T.
(2019).
SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution. 873-885.
-
Bhatia, E., Chacon, G., Pugsley, S., Teran, E., Gratz, P. V., & Jimenez, D. A.
(2019).
Perceptron-Based Prefetch Filtering. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
1-13.
-
Chou, C. C., Jung, J., Reddy, A., Gratz, P. V., & Voigt, D.
(2019).
vNVML: An Efficient User Space Library for Virtualizing and Sharing Non-Volatile Memories. 103-115.
-
Ramrakhyani, A., Gratz, P. V., & Krishna, T.
(2018).
Synchronized Progress in Interconnection Networks (SPIN) : A New Theory for Deadlock Freedom. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
699-711.
-
Fedorov, V., Kim, J., Qin, M., Gratz, P. V., & Reddy, A.
(2017).
Speculative Paging for Future NVM Storage. 399-410.
-
Reddy, M. P., Hadjitheophanous, S., Soteriou, V., Gratz, P. V., & Michael, M. K.
(2017).
Minimal Exercise Vector Generation for Reliability Improvement. 113-119.
-
Kim, J., Teran, E., Gratz, P. V., Jimenez, D. A., Pugsley, S. H., & Wilkerson, C.
(2017).
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. Operating Systems Review.
737-749.
-
Kim, J., Pugsley, S. H., Gratz, P. V., Reddy, A., Wilkerson, C., & Chishti, Z.
(2016).
Path Confidence based Lookahead Prefetching. Micro -Annual Workshop then Annual International Symposium-.
1-12.
-
Vitkovskiy, A., Soteriou, V., & Gratz, P. V.
(2015).
Clotho: Proactive Wearout Deceleration in Chip-Multiprocessor Interconnects. 117-124.
-
Kim, J., Fedorov, V., Gratz, P. V., & Reddy, A.
(2015).
Dynamic Memory Pressure Aware Ballooning. 103-112.
-
Targhetta, A. D., Owen, D., Israel, F. L., & Gratz, P. V.
(2015).
Energy-Efficient Implementations of GF(p) and GF(2m) Elliptic Curve Cryptography. 704-711.
-
Fedorov, V. V., Reddy, A., & Gratz, P. V.
(2015).
Shared Last-Level Caches and The Case for Longer Timeslices. 113-120.
-
Vitkovski, A., Soteriou, V., & Gratz, P. V.
(2015).
Wear-Aware Adaptive Routing for Networks-on-Chips. 1-2.
-
Won, J., Gratz, P., Shakkottai, S., & Hu, J.
(2015).
Having Your Cake and Eating It Too: Energy Savings without Performance Loss through Resource Sharing Driven Power Management. Proceedings of the International Symposium on Low Power Electronics and Design.
255-260.
-
Kadjo, D., Ayoub, R., Kishinevsky, M., & Gratz, P. V.
(2015).
A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms
-
Jang, H., Kim, J., Gratz, P., Yum, K. H., & Kim, E. J.
(2015).
Bandwidth-Efficient On-Chip Interconnect Designs for GPGPUs. Design Automation Conference.
1-6.
-
McHale, L., Casey, J., Gratz, P. V., & Sprintson, A.
(2014).
Stochastic Pre-Classification for SDN Data Plane Matching. Proceedings - International Conference on Network Protocols, ICNP.
596-602.
-
Fatehi, E., & Gratz, P. V.
(2014).
ILP and TLP in shared memory applications
-
Targhetta, A. D., Owen, D., & Gratz, P. V.
(2014).
The Design Space of Ultra-low Energy Asymmetric Cryptography. 55-65.
-
Won, J., Chen, X. i., Gratz, P., Hu, J., & Soteriou, V.
(2014).
Up By Their Bootstraps: Online Learning in Artificial Neural Networks for CMP Uncore Power Management. Proceedings - International Symposium on High-Performance Computer Architecture.
308-319.
-
Kadjo, D., Kim, J., Sharma, P., Panda, R., Gratz, P., & Jimenez, D.
(2014).
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors. Micro -Annual Workshop then Annual International Symposium-.
623-634.
-
Rasheed, S., Gratz, P. V., Shakkottai, S., & Hu, J.
(2014).
STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip. 176-177.
-
Kadjo, D., Ogras, U., Ayoub, R., Kishinevsky, M., & Gratz, P.
(2014).
Towards Platform Level Power Management in Mobile Systems. International System on Chip Conference.
146-151.
-
Kim, H., Vitkovskiy, A., Gratz, P. V., & Soteriou, V.
(2013).
Use it or lose it. 136-147.
-
Kadjo, D., Kim, H., Gratz, P., Hu, J., & Ayoub, R.
(2013).
Power Gating with Block Migration in Chip-Multiprocessor Last-Level Caches. 93-99.
-
Ramakrishna, M., Gratz, P. V., & Sprintson, A.
(2013).
GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip. 1-8.
-
Kumar, R., Deshpande, H., Choi, G., Sprintson, A., & Gratz, P.
(2013).
Bidirectional Interconnect Design for Low Latency High Bandwidth NoC. 215-218.
-
Chen, X. i., Xu, Z., Kim, H., Gratz, P. V., Hu, J., Kishinevsky, M., Ogras, U., & Ayoub, R.
(2013).
Dynamic voltage and frequency scaling for shared resources in multicore processor designs. 114.
-
Browning, M., Li, C., Gratz, P. V., & Palermo, S.
(2013).
LumiNOC: A Low-latency, High-Bandwidth per Watt, Photonic Network-on-Chip. 1-4.
-
Ghoshal, P., Casey, C. J., Gratz, P. V., & Sprintson, A.
(2013).
Stochastic Pre-Classification for Software Defined Firewalls. Proceedings - International Conference on Computer Communications and Networks, ICCCN.
1-8.
-
Chen, X. i., Xu, Z., Kim, H., Gratz, P., Hu, J., Kishinevsky, M., & Ogras, U.
(2012).
In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches. 43-50.
-
Li, C., Browning, M., Gratz, P. V., & Palermo, S.
(2012).
Energy-efficient Optical Broadcast for Nanophotonic Networks-on-Chip. 64-65.
-
Yang, Y. S., Deshpande, H., Choi, G., & Gratz, P.
(2012).
Exploiting Path Diversity for Low-Latency and High-Bandwidth with the Dual-path NoC Router. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
2433-2436.
-
Li, C., Browning, M., Gratz, P. V., & Palermo, S.
(2012).
LumiNOC. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
421-422.
-
Yang, Y. S., Kumar, R., Choi, G., & Gratz, P.
(2012).
WaveSync: A Low-Latency Source Synchronous Bypass Network-On-Chip Architecture. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
241-248.
-
Kim, H., Ghoshal, P., Grot, B., Gratz, P. V., & Jimnez, D. A.
(2011).
Reducing Network-on-Chip energy consumption through spatial locality speculation. 233-240.
-
Lotlikar, S., Pai, V., & Gratz, P. V.
(2011).
AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation. Proceedings of the IEEE International Conference on VLSI Design.
147-152.
-
Jain, T., Gratz, P. V., Sprintson, A., & Choi, G.
(2010).
Asynchronous Bypass Channels: Improving Performance for Multi-Synchronous NoCs. 51-58.
-
Gebhart, M., Maher, B. A., Coons, K. E., Diamond, J., Gratz, P., Marino, M., ... McKinley, K. S.
(2009).
An evaluation of the TRIPS computer system. ACM SIGPLAN NOTICES.
1-12.
-
Gebhart, M., Maher, B. A., Coons, K. E., Diamond, J., Gratz, P., Marino, M., ... McKinley, K. S.
(2009).
An evaluation of the TRIPS computer system. ACM SIGPLAN NOTICES.
1-12.
-
Gratz, P., Grot, B., & Keckler, S. W.
(2008).
Regional Congestion Awareness for Load Balance in Networks-on-Chip. Proceedings - International Symposium on High-Performance Computer Architecture.
203-214.
-
Gratz, P., Grot, B., & Keckler, S. W.
(2008).
Regional Congestion Awareness for Load Balance in Networks-on-Chip. Proceedings - International Symposium on High-Performance Computer Architecture.
186-+.
-
Gratz, P., Sankaralingam, K., Hanson, H., Shivakumar, P., McDonald, R., Keckler, S. W., & Burger, D.
(2007).
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
-
Sankaralingam, K., Nagarajan, R., McDonald, R., Desikan, R., Drolia, S., Govindan, M. S., ... Burger, D.
(2006).
Distributed microarchitectural protocols in the TRIPS prototype processor. Micro -Annual Workshop then Annual International Symposium-.
480-+.
-
Gratz, P., Kim, C., McDonald, R., Keckler, S. W., & Burger, D.
(2006).
Implementation and Evaluation of On-Chip Network Architectures. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
477-484.
-
Chacon, G., Gober, N., Nathella, K., Gratz, P. V., & Jimenez, D. A.
(2023).
A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end. 61-70.
-
institutional repository document
-
McHale, L., Gratz, P. V., & Sprintson, A.
(2023).
Flow Correlator: A Flow Table Cache Management Strategy
-
Barboza, E. C., Ketkar, M., Kishinevsky, M., Gratz, P., & Hu, J.
(2023).
Machine Learning for Microprocessor Performance Bug Localization
-
Gober, N., Chacon, G., Wang, L., Gratz, P. V., Jimenez, D. A., Teran, E., Pugsley, S., & Kim, J.
(2022).
The Championship Simulator: Architectural Simulation for Education and Competition
-
Chacon, G. A., Williams, C., Knechtel, J., Sinanoglu, O., & Gratz, P. V.
(2022).
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems
-
Tirumalasetty, C., Chou, C. C., Reddy, N., Gratz, P., & Abouelwafa, A.
(2021).
Reducing Minor Page Fault Overheads through Enhanced Page Walker
-
Chacon, G., Mandal, T., Knechtel, J., Sinanoglu, O., Gratz, P., & Soteriou, V.
(2021).
Coherence Attacks and Countermeasures in Interposer-Based Systems
-
Barboza, E. C., Jacob, S., Ketkar, M., Kishinevsky, M., Gratz, P., & Hu, J.
(2020).
Automatic Microprocessor Performance Bug Detection
-
Wen, F., Qin, M., Gratz, P. V., & Reddy, A.
(2020).
FPGA-based Hyrbid Memory Emulation System
-
Wen, F., Qin, M., Gratz, P., & Reddy, N.
(2020).
Hardware Memory Management for Future Mobile Hybrid Memory Systems
-
McHale, L., Gratz, P. V., & Sprintson, A.
(2023).
Flow Correlator: A Flow Table Cache Management Strategy
-
patent
-
Annapareddy, N. R., Chou, C., Tirumulasetty, C., Gratz, P., & Abouelwafa, A.
Methods, Systems, And Computer Readable Media For Performing Page Fault Handling
-
Annapareddy, N. R., Chou, C., Tirumulasetty, C., Gratz, P., & Abouelwafa, A.
Methods, Systems, And Computer Readable Media For Performing Page Fault Handling
Research
principal investigator on
- FoMR: Secure, Light-Weight Speculative Engines for Coordinated and Cohesive Speculation in Future Memory Systems awarded by National Science Foundation - (Arlington, Virginia, United States) 2018 - 2021
- SHF: Small: Emerging Memory Architectures for Big Memory Applications-- awarded by National Science Foundation - (Arlington, Virginia, United States) 2013 - 2017
co-principal investigator on
Teaching
teaching activities
- CSCE491 Hnr-research Instructor
- CSCE491 Hnr-research Instructor
- CSCE684 Professional Internship: In-ab Instructor
- CSCE691 Research Instructor
- ECEN350 Comp Arch & Design-australia Instructor
- ECEN350 Computer Arch & Design Instructor
- ECEN404 Electrical Design Lab Ii Instructor
- ECEN449 Microprocsr Sys Dsgn Instructor
- ECEN469 Adv Computer Architec: Bel Instructor
- ECEN469 Adv Computer Architec: Gbr Instructor
- ECEN469 Adv Computer Architec:uk Instructor
- ECEN485 Directed Studies Instructor
- ECEN491 Research Instructor
- ECEN676 Adv Computer Architec Instructor
- ECEN681 Seminar-ce Instructor
- ECEN684 Professional Internship Instructor
- ECEN684 Professional Internship: In-ab Instructor
- ECEN685 Directed Studies Instructor
- ECEN689 Sptp: Processor Mem Systems Instructor
- ECEN691 Research Instructor
- ECEN749 Microprocessor Systems Design Instructor
Works By Students
chaired theses and dissertations
-
Albarakat, Laith Mohammad (2017-07). Multithreading Aware Hardware Prefetching for Chip Multiprocessors.
-
Boga, Siva Bhanu (2015-07). Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors.
-
Chen, Guangming (2013-05). SPAcENoCs : A Scalable Platform for FPGA Accelerated Emulator of NoCs.
-
Chen, Xi (2013-05). Physical Planning and Uncore Power Management for Multi-Core Processors.
-
Elliott, Lee Bryan (2018-07). Utilizing Criticality Stacks for Dynamic Voltage and Frequency Scaling.
-
Fatehi, Ehsan (2015-04). ILP and TLP in Shared Memory Applications: A Limit Study.
-
Ghoshal, Pritha (2012-12). Low Latency Stochastic Filtering Software Firewall Architecture.
-
Girdhar, Nimish (2016-07). Predicting Thread Criticality and Frequency Scalability for Active Load Balancing in Shared Memory Multithreaded Applications.
-
Gu, Haiyin (2011-08). VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs.
-
Jain, Tushar Naveen Kumar (2010-08). Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips.
-
Jayabalan, Jagadish (2012-08). Handshake and Circulation Flow Control in Nanaphotonic Interconnects.
-
Kadjo, David (2015-05). Energy Efficiency and Performance in Multiprocessors Systems on Chip.
-
Kim, Hyungjun (2013-08). Energy and Reliability in Future NOC Interconnected CMPS.
-
Kim, Jinchun (2017-05). Reference Speculation-driven Memory Management.
-
Kodati, Vamsi Krishna (2015-11). Probability-Based Memory Access Controller (PMAC) for Energy Reduction in High Performance Processors.
-
Lotlikar, Swapnil Subhash (2010-08). Design, Implementation and Evaluation of a Configurable NoC for AcENoCs FPGA Accelerated Emulation Platform.
-
Mahadevuni, Amarnath (2018-03). Autonomous Navigation Using Reinforcement Learning with Spiking Neural Networks.
-
Naranjo Carmona, Alberto Javier (2014-12). Improving the Simulation Environment for Computer Architecture.
-
Narayana, Sagar 1986- (2012-12). Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.
-
Ni, Ruixiao (2014-01). On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs.
-
Pai, Vinayak (2010-12). HW/SW Codesign and Design, Evaluation of Software Framework for AcENoCs : An FPGA-Accelerated NoC Emulation Platform.
-
Panda, Reena (2011-12). A Branch-Directed Data Cache Prefetching Technique for Inorder Processors.
-
Pappireddy, Madhukarreddy (2016-08). PRITEXT: Processor Reliability Improvement Through Exercise Technique.
-
Prabhu, Subodh (2010-05). Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization.
-
Ramakrishna, Mukund (2012-08). GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip.
-
Rasheed, Shalimar (2014-04). A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.
-
Shankar, Anusha (2014-12). Lock Prediction to Reduce the Overhead of Synchronization Primitives.
-
Sharma, Prabal (2013-08). A Branch Predictor Directed Data Cache Prefetcher for Out-of-order and Multicore Processors.
-
Soni, Tarun (2010-08). Mobile Home Node: Improving Directory Cache Coherence Performance in NoCs via Exploitation of Producer-Consumer Relationships.
-
Targhetta, Andrew David (2015-05). The Design Space of Ultra-low Energy Asymmetric Cryptography.
-
Won, Jae Yeon (2015-08). Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs.
Background
education and training
- Ph.D. in Electrical and Computer Engineering, The University of Texas at Austin - (Austin, Texas, United States) 2008
- M.S. in Electrical and Computer Engineering, University of Florida - (Gainesville, Florida, United States) 1997
- B.S. in Electrical and Computer Engineering, University of Florida - (Gainesville, Florida, United States) 1994
awards and honors
Contact
first name
- Paul
has last name
- Gratz
mailing address
-
Texas A&M University
Electrical Engineering
3128 TAMU
College Station, TX 77843-3128
USA
Other
- pgratz@gratz1.com