LumiNOC
Conference Paper
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Overview
abstract
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Achieving scaling performance as core counts increase to the hundreds in future chip-multi-processors (CMPs) requires high performing, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nano-photonic NoC architecture, LumiNOC, optimized for high performance and power-efficiency. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50% lower latency at low loads and 40% higher throughput per Watt on synthetic traffic, versus other reported photonic NoCs. LumiNOC reduces latencies 40% versus an electrical 2D mesh NoCs on the PARSEC shared memory, multithreaded benchmark suite. Copyright © 2012 by the Association for Computing Machinery, Inc. (ACM).
name of conference
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the 21st international conference
published proceedings
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2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)
author list (cited authors)
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Li, C., Browning, M., Gratz, P. V., & Palermo, S
citation count
complete list of authors
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Li, Cheng||Browning, Mark||Gratz, Paul V||Palermo, Samuel
publisher
published in
Research
keywords
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Cmp
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Noc
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Power Efficiency
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Synthetic/realistic Workload
Identity
Digital Object Identifier (DOI)
International Standard Book Number (ISBN) 13
Additional Document Info
Other
user-defined tag
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7 Affordable and Clean Energy