publication venue for
- Boolean Formula-based Branch Prediction for Future Technologies. 97-106. 2001
- Message from the Program Co-Chairs 2016
- POSTER: Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip 2016
- Message from the Program Co-Chairs 2016
- An Algorithmic Approach to Communication Reduction in Parallel Graph Algorithms 2015
- From Petascale to the Pocket: Adaptively Scaling Parallel Programs for Mobile SoCs 2014
- KLA: A New Algorithmic Paradigm for Parallel Graph Computations 2014
- Processing Big Data Graphs on Memory-Restricted Systems 2014
- APCR: An Adaptive Physical Channel Regulator for On-Chip Interconnects 2012
- LumiNOC 2012
- Message from the General Chair 2011
- Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy 2011
- Decoupled Cache Segmentation: Mutable Policy with Automated Bypass 2011
- Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback 2011
- Program Interferometry 2011
- Scalable and Efficient Bounds Checking for Large-Scale CMP Environments 2011
- Using dead blocks as a virtual victim cache 2010
- A flexible heterogeneous multi-core architecture 2007
- I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems 2007
- Message from the Program Chair 2007
- The STAPL pArray 2007
- A Flexible Heterogeneous Multi-Core Architecture 2007
- Region array SSA 2006
- The value evolution graph and its use in memory reference analysis 2004
- An Adaptive Algorithm Selection Framework**Research was performed at Texas A&M and supported in part by NSF CAREER Award CCR-9734471, NSF Grant ACI-9872126, NSF Grant EIA-0103742, NSF Grant ACI-0326350, NSF Grant ACI-0113971, DOE ASCI ASAP Level 2 Grant B347886 2004
- Using software logging to support multi-version buffering in thread-level speculation 2003
- Architectural support for parallel reductions in scalable shared-memory multiprocessors 2001