12TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS
Journal
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Overview
publication venue for
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Boolean Formula-based Branch Prediction for Future Technologies.
97-106.
2001
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Message from the Program Co-Chairs
2016
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POSTER
2016
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Message from the Program Co-Chairs
2016
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An Algorithmic Approach to Communication Reduction in Parallel Graph Algorithms
2015
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From Petascale to the Pocket
2014
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ILP and TLP in shared memory applications
2014
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KLA: A New Algorithmic Paradigm for Parallel Graph Computations
2014
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Processing Big Data Graphs on Memory-Restricted Systems
2014
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APCR: an adaptive physical channel regulator for on-chip interconnects
2012
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LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures
2012
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Decoupled Cache Segmentation: Mutable Policy with Automated Bypass
2011
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Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback
2011
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Message from the General Chair
2011
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Program Interferometry
2011
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Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy
2011
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Scalable and Efficient Bounds Checking for Large-Scale CMP Environments
2011
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Using dead blocks as a virtual victim cache
2010
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A flexible heterogeneous multi-core architecture
2007
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Drug design on the Cell BroadBand Engine
2007
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I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems
2007
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Message from the Program Chair
2007
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The STAPL pArray
2007
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Region array SSA
2006
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The value evolution graph and its use in memory reference analysis
2004
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An Adaptive Algorithm Selection Framework**Research was performed at Texas A&M and supported in part by NSF CAREER Award CCR-9734471, NSF Grant ACI-9872126, NSF Grant EIA-0103742, NSF Grant ACI-0326350, NSF Grant ACI-0113971, DOE ASCI ASAP Level 2 Grant B347886
2004
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Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation **This work was supported in part by the National Science Foundation under grants EIA-0081307, EIA-0072102, and EIA-0103741; DARPA under grant F30602–01-C-0078; DOE under grant B347886; Ministry of Education of Spain under grant TIC 2001–0995-C02–02; and gifts from IBM, Intel and HP.
2003
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Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors
2001
Identity
International Standard Serial Number (ISSN)
