Architectural support for parallel reductions in scalable shared-memory multiprocessors Conference Paper

abstract

• Reductions are important and time-consuming operations in many scientific codes. Effective parallelization of reductions is a critical transformation for loop parallelization, especially for sparse, dynamic applications. Unfortunately, conventional reduction parallelization algorithms are not scalable. In this paper, we present new architectural support that significantly speeds-up parallel reduction and makes it scalable in shared-memory multiprocessors. The required architectural changes are mostly confined to the directory controllers. Experimental results based on simulations show that the proposed support is very effective. While conventional software-only reduction parallelization delivers average speedups of only 2.7 for 16 processors, our scheme delivers average speedups of 7.6.

name of conference

• Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques

authors

• Rauchwerger, Lawrence

published proceedings

• 2001 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS

author list (cited authors)

• Garzaran, M. J., Prvulovic, M., Zhang, Y., Jula, A., Yu, H., Rauchwerger, L., & Torrellas, J.

citation count

• 11

complete list of authors

• Garzaran, MJ||Prvulovic, M||Zhang, Y||Jula, A||Yu, H||Rauchwerger, L||Torrellas, J

publication date

• January 2001

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT  Journal

keywords

• 33 Built Environment And Design
• 3301 Architecture

Digital Object Identifier (DOI)

• 10.1109/PACT.2001.953304

International Standard Book Number (ISBN) 10

• 0-7695-1363-8

start page

• 243

end page

• 254

URL

• http://dx.doi.org/10.1109/pact.2001.953304