Distributed Microarchitectural Protocols in the TRIPS Prototype Processor Conference Paper uri icon

abstract

  • Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched micronetworks. Since large processor cores will require multiple clock cycles to traverse, control must be distributed, not centralized. This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution. It details each of the five types of reused tiles that compose the processor, the control and data networks that connect them, and the distributed microarchitectural protocols that implement instruction fetch, execution, flush, and commit. We also describe the physical design issues that arose when implementing the microarchitecture in a 170M transistor, 130nm ASIC prototype chip composed of two 16-wide issue distributed processor cores and a distributed 1MB nonuniform (NUCA) on-chip memory system. 2006 IEEE.

name of conference

  • 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

published proceedings

  • 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

altmetric score

  • 6

author list (cited authors)

  • Sankaralingam, K., Nagarajan, R., McDonald, R., Desikan, R., Drolia, S., Govindan, M. S., ... Burger, D.

citation count

  • 110

complete list of authors

  • Sankaralingam, Karthikeyan||Nagarajan, Ramadass||McDonald, Robert||Desikan, Rajagopalan||Drolia, Saurabh||Govindan, MS||Gratz, Paul||Gulati, Divya||Hanson, Heather||Kim, Changkyu||Liu, Haiming||Ranganathan, Nitya||Sethumadhavan, Simha||Sharif, Sadia||Shivakumar, Premkishore||Keckler, Stephen||Burger, Doug

publication date

  • December 2006

publisher