Implementation and Evaluation of On-Chip Network Architectures Conference Paper uri icon

abstract

  • Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is occurring in on-chip interconnect. This paper presents the design, implementation and evaluation of one such on-chip network, the TRIPS OCN. The OCN is a wormhole routed, 4×10, 2D mesh network with four virtual channels. It provides a high bandwidth, low latency interconnect between the TRIPS processors, L2 cache banks and I/O units. We discuss the tradeoffs made in the design of the OCN, in particular why area and complexity were traded off against latency. We then evaluate the OCN using synthetic as well as realistic loads. We found that synthetic benchmarks do not provide sufficient indication of the behavior of realistic loads on this network. Finally, we examine the effect of link bandwidth and router FIFO depth on overall performance. © 2006 IEEE.

name of conference

  • 2006 International Conference on Computer Design

published proceedings

  • 2006 International Conference on Computer Design

author list (cited authors)

  • Gratz, P., Kim, C., McDonald, R., Keckler, S. W., & Burger, D

citation count

  • 129

complete list of authors

  • Gratz, Paul||Kim, Changkyu||McDonald, Robert||Keckler, Stephen W||Burger, Doug

publication date

  • October 2006

publisher