Chen, Guangming (2013-05). SPAcENoCs : A Scalable Platform for FPGA Accelerated Emulator of NoCs. Master's Thesis. Thesis uri icon

abstract

  • The majority of modern high performance computing systems have employed on-chip multi-processors. As the number of on-chip cores soars, the traditional non- scalable communication infrastructures, commonly observed as shared buses or cross- bars, no longer accommodate the increasing communication demand by the modern multi-core chips. The newly emerging Network-On-Chip (NoC) interconnection scheme has provided a scalable, robust and power-efficient solution that also satisfies the requirements on both bandwidth and latency. A tool that enables swift exploration of the vast NoC design space is then in great demand to meet the stiff time pressure over research and development. Based on the work of AcENoCs, an NoC simulator designed on the basis of software and hardware codesign seeking for a large simulatable network size, the SPAcENoCs (Scalable Platform for FPGA Accelerated Emulator of NoCs) employs the Time-Division Multiplexing (TDM) techniques to implement a simulator for even larger NoCs without sacrificing simulation speed and cycle accuracy which have been highlighted in the work of AcENoCs. This paper will focus on re-organization of the given software/hardware codesigned frameworks so that the TDM techniques may be applied. While both frameworks require re-design, the major efforts involve re- construction of the hardware framework by adding data buffers and affiliated logic to ensure the data generated in different time divisions are properly preserved and trans- mitted. Various design tradeoffs over hardware budget and simulation performance are also discussed and attempted in this paper. During the development process, the techniques of device virtualization and generic programming are introduced to overcome the verification challenges that are commonly seen in software/hardware codesigned systems. The synthesis results of various design options suggested that the simulation of a 9 x 6 network, more than twice the size of largest applicable size in AcENoCs, can be accommodated by the device. Based on the simulation result of AcENoCs, the estimated speedup of SPAcENoCs over software simulator for the 9 x 6 NoC is around 28-94X, twice the one achieved by AcENoCs in a smaller network.
  • The majority of modern high performance computing systems have employed on-chip multi-processors. As the number of on-chip cores soars, the traditional non- scalable communication infrastructures, commonly observed as shared buses or cross- bars, no longer accommodate the increasing communication demand by the modern multi-core chips. The newly emerging Network-On-Chip (NoC) interconnection scheme has provided a scalable, robust and power-efficient solution that also satisfies the requirements on both bandwidth and latency. A tool that enables swift exploration of the vast NoC design space is then in great demand to meet the stiff time pressure over research and development.

    Based on the work of AcENoCs, an NoC simulator designed on the basis of software and hardware codesign seeking for a large simulatable network size, the SPAcENoCs (Scalable Platform for FPGA Accelerated Emulator of NoCs) employs the Time-Division Multiplexing (TDM) techniques to implement a simulator for even larger NoCs without sacrificing simulation speed and cycle accuracy which have been highlighted in the work of AcENoCs. This paper will focus on re-organization of the given software/hardware codesigned frameworks so that the TDM techniques may be applied. While both frameworks require re-design, the major efforts involve re- construction of the hardware framework by adding data buffers and affiliated logic to ensure the data generated in different time divisions are properly preserved and trans- mitted. Various design tradeoffs over hardware budget and simulation performance are also discussed and attempted in this paper. During the development process, the techniques of device virtualization and generic programming are introduced to overcome the verification challenges that are commonly seen in software/hardware codesigned systems.

    The synthesis results of various design options suggested that the simulation of a 9 x 6 network, more than twice the size of largest applicable size in AcENoCs, can be accommodated by the device. Based on the simulation result of AcENoCs, the estimated speedup of SPAcENoCs over software simulator for the 9 x 6 NoC is around 28-94X, twice the one achieved by AcENoCs in a smaller network.

publication date

  • May 2013