ARI Academic Article uri icon

abstract

  • Decreasing the traffic from the CPU LLC to main memory is a very important issue in modern systems. Recent work focuses on cache misses, overlooking the impact of writebacks on the total memory traffic, energy consumption, IPC, and so forth. Policies that foster a balanced approach, between reducing write traffic to memory and improving miss rates, can increase overall performance and improve energy efficiency and memory system lifetime for NVM memory technology, such as phase-change memory (PCM). We propose Adaptive Replacement and Insertion (ARI), an adaptive approach to last-level CPU cache management, optimizing the two parameters (miss rate and writeback rate) simultaneously. Our specific focus is to reduce writebacks as much as possible while maintaining or improving the miss rate relative to conventional LRU replacement policy. ARI reduces LLC writebacks by 33%, on average, while also decreasing misses by 4.7%, on average. In a typical system, this boosts IPC by 4.9%, on average, while decreasing energy consumption by 8.9%. These results are achieved with minimal hardware overheads.

published proceedings

  • ACM Transactions on Architecture and Code Optimization

author list (cited authors)

  • Fedorov, V. V., Qiu, S., Reddy, A., & Gratz, P. V

citation count

  • 16

complete list of authors

  • Fedorov, Viacheslav V||Qiu, Sheng||Reddy, AL Narasimha||Gratz, Paul V

publication date

  • December 2013