LumiNOC: A Low-latency, High-Bandwidth per Watt, Photonic Network-on-Chip
Conference Paper
Overview
Research
Identity
Additional Document Info
Other
View All
Overview
abstract
To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip - multi-processors (CMPs), internally interconnected via networks - on-chip (NoC) to meet growing communication needs. Achieving scaling performance as core counts increase to the hundreds in future CMPs, however, will require high performance, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nanophotonic NoC architecture, LumiNOC, optimized for high performance and power-efficiency. This paper makes three primary contributions: a novel, nanophotonic architecture which partitions the network in to subnets for better efficiency; a purely photonic, in-band, distributed arbitration scheme; and a channel sharing arrangement utilizing the same waveguides and wavelengths for arbitration as data transmission. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50% lower latency at low loads and 40% higher throughput per Watt on synthetic traffic, versus other reported photonic NoCs. LumiNOC reduces latencies 40% versus an electrical 2D mesh NoCs on the PARSEC shared-memory, multithreaded benchmark suite. 2013 IEEE.
name of conference
2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
