SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing
-
- Overview
-
- Research
-
- Identity
-
- Additional Document Info
-
- Other
-
- View All
-
Overview
published proceedings
-
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
author list (cited authors)
-
Yang, Y. S., Deshpande, H., Choi, G., & Gratz, P. V.
citation count
complete list of authors
-
Yang, Yoon Seok||Deshpande, Hrishikesh||Choi, Gwan||Gratz, Paul V
publication date
publisher
published in
Research
keywords
-
Interconnect Architecture
-
On-chip Interconnect
-
Packet Latency
-
Path Diversity
-
Router Design
-
Simultaneous Dual-path Routing (sdpr)
Identity
Digital Object Identifier (DOI)
Additional Document Info
start page
end page
volume
issue
Other
URL
-
http://dx.doi.org/10.1109/tcad.2016.2570428
user-defined tag
-
7 Affordable and Clean Energy