SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing Academic Article

authors

• Gratz, Paul

published proceedings

• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

author list (cited authors)

• Yang, Y. S., Deshpande, H., Choi, G., & Gratz, P. V.

citation count

• 6

complete list of authors

• Yang, Yoon Seok||Deshpande, Hrishikesh||Choi, Gwan||Gratz, Paul V

publication date

• March 2018

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems  Journal

keywords

• Interconnect Architecture
• On-chip Interconnect
• Packet Latency
• Path Diversity
• Router Design
• Simultaneous Dual-path Routing (sdpr)

Digital Object Identifier (DOI)

• 10.1109/TCAD.2016.2570428

start page

• 545

end page

• 558

volume

• 37

issue

• 3

URL

• http://dx.doi.org/10.1109/tcad.2016.2570428

user-defined tag

• 7 Affordable and Clean Energy