B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors Academic Article

abstract

• Computer architecture is beset by two opposing trends. Technology scaling and deep pipelining have led to high memory access latencies; meanwhile, power and energy considerations have revived interest in traditional in-order processors. In-order processors, unlike their superscalar counterparts, do not allow execution to continue around data cache misses. In-order processors, therefore, suffer a greater performance penalty in the light of the current high memory access latencies. Memory prefetching is an established technique to reduce the incidence of cache misses and improve performance. In this paper, we introduce B-Fetch, a new technique for data prefetching which combines branch prediction based lookahead deep path speculation with effective address speculation, to efficiently improve performance in in-order processors. Our results show that B-Fetch improves performance 38.8% on SPEC CPU2006 benchmarks, beating a current, state-of-the-art prefetcher design at 1/3 the hardware overhead. 2011 Published by the IEEE Computer Society.

authors

• Gratz, Paul
• Jimenez, Daniel

published proceedings

• IEEE COMPUTER ARCHITECTURE LETTERS

author list (cited authors)

• Panda, R., Gratz, P. V., & Jimenez, D. A.

citation count

• 14

complete list of authors

• Panda, Reena||Gratz, Paul V||Jimenez, Daniel A

publication date

• July 2012

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Computer Architecture Letters  Journal

keywords

• Branch Prediction
• Data Cache Prefetching
• In-order Processors
• Memory Systems
• Value Prediction

Digital Object Identifier (DOI)

• 10.1109/L-CA.2011.33

start page

• 41

end page

• 44

volume

• 11

issue

• 2

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fl-ca.2011.33