HR job title
- Professor
- Contact Info
- 1 979 845 1858
- Websites
Jimenez, Daniel Professor
Positions
- Professor - Term Appointment, Computer Science and Engineering, College of Engineering
I'm interested in anything related to making computation go faster. My focus is on microarchitecture and the interaction between the compiler and the microarchitecture. I've been doing a lot of work in branch prediction and more recently caches. I'm known for inventing the perceptron branch predictor as well as for other research.
Research Areas
- Overview
- Publications
- Research
- Teaching
- Works By Students
- Background
- Contact
- Other
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Overview
Publications
selected publications
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academicarticle
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Jimenez, D. A.
(2021).
Top Picks From the 2020 Computer Architecture Conferences. IEEE Micro.
41(3), 6-9.
-
Chen, L., Penney, D., & Jimnez, D.
(2020).
AI for Computer Architecture. Synthesis Lectures on Computer Architecture.
15(5), 1-142.
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AlBarakat, L. M., Gratz, P. V., & Jimenez, D. A.
(2018).
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. IEEE Computer Architecture Letters.
17(2), 175-178.
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Kim, J., Teran, E., Gratz, P. V., Jimenez, D. A., Pugsley, S. H., & Wilkerson, C.
(2017).
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. ACM SIGPLAN NOTICES.
52(4), 737-749.
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Liu, Q., Moreto, M., Abella, J., Cazorla, F. J., Jimenez, D. A., & Valero, M.
(2016).
Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Transactions on Architecture and Code Optimization (TACO).
12(4), 1-26.
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Kim, H., Grot, B., Gratz, P. V., & Jimenez, D. A.
(2014).
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. IEEE Transactions on Computers.
63(3), 543-556.
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Wang, X., Weng, L., Wang, Z., & Luo, Y.
(2013).
Revisiting memory management on virtualized environments. ACM Transactions on Architecture and Code Optimization (TACO).
10(4), 1-20.
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Tian, Y., Khan, S. M., & Jimenez, D. A.
(2013).
Temporal-Based Multilevel Correlating Inclusive Cache Replacement. ACM Transactions on Architecture and Code Optimization (TACO).
10(4), 1-24.
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Wang, Z., Shan, S., Cao, T., Gu, J., Xu, Y. i., Mu, S., Xie, Y., & Jimenez, D. A.
(2013).
WADE: Writeback-Aware Dynamic Cache Management for NVM-Based Main Memory System. ACM Transactions on Architecture and Code Optimization (TACO).
10(4), 1-21.
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Jimenez, D. A.
(2013).
IMPROVING MEMORY RELIABILITY, POWER AND PERFORMANCE USING MIXED-CELL DESIGNS
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Wang, Z., Khan, S. M., & Jimnez, D. A.
(2012).
Improving writeback efficiency with decoupled last-write prediction. Computer architecture news.
40(3), 309-320.
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Panda, R., Gratz, P. V., & Jimenez, D. A.
(2012).
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. IEEE Computer Architecture Letters.
11(2), 41-44.
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Jimenez, D. A.
(2011).
SNIP: Scaled Neural Indirect Predictor
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Jimnez, D. A.
(2009).
Generalizing neural branch prediction. ACM Transactions on Architecture and Code Optimization (TACO).
5(4), 17-27.
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Perics, M., Cristal, A., Cazorla, F. J., Gonzlez, R., Veidenbaum, A., Jimnez, D. A., & Valero, M.
(2008).
A Two-Level Load/Store Queue Based on Execution Locality. Computer architecture news.
36(3), 25-36.
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Loh, G. H., & Jimnez, D. A.
(2008).
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. International Journal of Parallel Programming.
36(2), 267-286.
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Hu, C., Jimenez, D. A., & Kremer, U.
(2007).
An evaluation infrastructure for power and energy optimisations. International Journal of Embedded Systems.
3(1/2), 31-31.
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Hu, C., McCabe, J., Jimnez, D. A., & Kremer, U.
(2005).
The Camino Compiler infrastructure. Computer architecture news.
33(5), 3-8.
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Jimnez, D. A.
(2005).
Code placement for improving dynamic branch prediction accuracy. ACM SIGPLAN NOTICES.
40(6), 107-116.
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Jimnez, D. A.
(2005).
Improved latency and accuracy for neural branch prediction. ACM TRANSACTIONS ON GRAPHICS.
23(2), 197-218.
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Jimenez, D. A.
(2005).
Piecewise Linear Branch Prediction. Computer architecture news.
33(2), 382-393.
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Jimnez, D. A.
(2005).
Idealized piecewise linear branch prediction. 7.
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Jimenez, D. A.
(2004).
The C-Breeze compiler infrastructure
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Jimnez, D. A., & Lin, C.
(2002).
Neural methods for dynamic branch prediction. ACM TRANSACTIONS ON GRAPHICS.
20(4), 369-397.
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Jimenez, D. A.
(2002).
Combining hyperblocks and exit prediction to increase front-end bandwidth and performance
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Jimenez, D. A., Hanson, H. L., & Lint, C.
(2001).
Boolean Formula-based Branch Prediction for Future Technologies. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
97-106.
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Jimenez, D. A.
A Method for Locating BK Anatomical Landmarks for a Laser Scanning Imager
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Jimenez, D. A.
Enabling High-Performance, Mixed-Signal Approximate Computing
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Jimenez, D. A.
Enhancing Signature Path Prefetching with Perceptron Prefetch Filtering
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Jimenez, D. A.
OH-SNAP: Optimized Hybrid Scaled Neural Analog Predictor
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Jimenez, D. A.
Perceptrons for Dummies
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Jimenez, D. A.
Program Phase Classification for Power Behavior Characterization
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Jimenez, D. A.
State-of-the-art graphic processing units (GPUs) can offer very high computational throughput for highly parallel applications using hundreds of integrated cores. In general, the peak throughput of a GPU is proportional to the product of the number of cores and their frequency. However, the product is often limited by a power constraint. Although the throughput can be increased with more cores for... chapter
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Jimenez, D. A.
Workshop on Advancing Computer Architecture Research (ACAR-II) Laying a New Foundation for IT_ Computer Architecture for 2025 and Beyond
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Jimenez, D. A.
(2021).
Top Picks From the 2020 Computer Architecture Conferences. IEEE Micro.
41(3), 6-9.
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conference paper
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Vavouliotis, G., Chacon, G., Alvarez, L., Gratz, P. V., Jimenez, D. A., & Casas, M.
(2022).
Page Size Aware Cache Prefetching. Micro -Annual Workshop then Annual International Symposium-.
956-974.
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Khan, T. A., Ugur, M., Nathellat, K., Sunwoot, D., Litz, H., Jimenez, D. A., & Kasikci, B.
(2022).
Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications. Micro -Annual Workshop then Annual International Symposium-.
19-34.
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Song, S., Khan, T. A., Shahri, S. M., Sriraman, A., Soundararajan, N. K., Subramoney, S., ... Kasikci, B.
(2022).
Thermometer: Profile-Guided BTB Replacement for Data Center Applications. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
742-756.
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Vavouliotis, G., Alvarez, L., Grot, B., Jimnez, D., & Casas, M.
(2021).
Morrigan: A Composite Instruction TLB Prefetcher. 1138-1153.
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Vavouliotis, G., Alvarez, L., Karakostas, V., Nikas, K., Koziris, N., Jimenez, D. A., & Casas, M.
(2021).
Exploiting Page Table Locality for Agile TLB Prefetching. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
85-98.
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Jamet, A. V., Alvarez, L., Jimenez, D. A., & Casas, M.
(2020).
Characterizing the impact of last-level cache replacement policies on big-data workloads. 134-144.
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Mirbagher-Ajorpaz, S., Garza, E., Pokam, G., & Jimenez, D. A.
(2020).
CHIRP: Control-Flow History Reuse Prediction. 131-145.
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Mirbagher-Ajorpaz, S., Pokam, G., Mohammadian-Koruyeh, E., Garza, E., Abu-Ghazaleh, N., & Jimenez, D. A.
(2020).
PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron. 1124-1137.
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Jimenez, D. A.
(2020).
Support for Diverse Students. 3584-3584.
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AlBarakat, L. M., Gratz, P. V., & Jimnez, D. A.
(2020).
SB-Fetch. 1-12.
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Jimenez, D. A.
(2020).
Bara: Branch Agnostic Region Searching Algorithm
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Grayson, B., Rupley, J., Zuraski, G. J., Quinnell, E., Jimenez, D. A., Nakra, T., ... Ghiya, A.
(2020).
Evolution of the Samsung Exynos CPU Microarchitecture Industrial Product. Annual International Symposium on Computer Architecture.
40-51.
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Jimenez, D. A.
(2020).
Temporal Ancestry Prefetcher
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Backes, L., & Jimenez, D. A.
(2019).
The Impact of Cache Inclusion Policies on Cache Management Techniques. 428-438.
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Bhatia, E., Chacon, G., Pugsley, S., Teran, E., Gratz, P. V., & Jimenez, D. A.
(2019).
Perceptron-Based Prefetch Filtering. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
1-13.
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Garza, E., Mirbagher, S., Khan, T. A., & Jimenez, D. A.
(2019).
Bit-level Perceptron Prediction for Indirect Branches. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
27-38.
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Ajorpaz, S. M., Garza, E., Jindal, S., & Jimenez, D. A.
(2018).
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
519-532.
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Teran, E., Chishti, Z., Wang, Z., Wilkerson, C., & Jimenez, D. A.
(2018).
Flexible Associativity for DRAM Caches. 88-96.
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Jimenez, D. A., & Teran, E.
(2017).
Multiperspective Reuse Prediction. Micro -Annual Workshop then Annual International Symposium-.
436-448.
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Kim, J., Teran, E., Gratz, P. V., Jimenez, D. A., Pugsley, S. H., & Wilkerson, C.
(2017).
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. Operating Systems Review.
737-749.
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Jimenez, D. A.
(2017).
Machine learning for microarchitectural prediction
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Jimenez, D. A.
(2017).
Message from the Program Chair. Proceedings - International Symposium on High-Performance Computer Architecture.
xi-xii.
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Wang, Z., Jimenez, D. A., Zhang, T., Loh, G. H., & Xie, Y.
(2016).
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. Proceedings / Symposium on Computer Architecture and High Performance Computing. Symposium on Computer Architecture and High Performance Computing.
109-117.
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Teran, E., Wang, Z., & Jimenez, D. A.
(2016).
Perceptron Learning for Reuse Prediction. Micro -Annual Workshop then Annual International Symposium-.
1-12.
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Jimenez, D. A.
(2016).
Building a low latency, highly associative dram cache with the buffered way predictor
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Teran, E., Tian, Y., Wang, Z., & Jimenez, D. A.
(2016).
Minimal Disturbance Placement and Promotion. Proceedings - International Symposium on High-Performance Computer Architecture.
201-211.
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Jimenez, D. A.
(2016).
Multiperspective Perceptron Predictor with TAGE
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Jimenez, D. A.
(2016).
Multiperspective perceptron predictor
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Tian, Y., Puthoor, S., Greathouse, J. L., Beckmann, B. M., & Jimnez, D. A.
(2015).
Adaptive GPU cache bypassing. 25-35.
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Tian, Y., Khan, S. M., Jimenez, D. A., & Loh, G. H.
(2014).
Last-level Cache Deduplication. 53-62.
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Wang, Z., Jimenez, D. A., Xu, C., Sun, G., & Xie, Y.
(2014).
Adaptive Placement and Migration Policy for an STT-RAM-Based Hybrid Cache. Proceedings - International Symposium on High-Performance Computer Architecture.
13-24.
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Kadjo, D., Kim, J., Sharma, P., Panda, R., Gratz, P., & Jimenez, D.
(2014).
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors. Micro -Annual Workshop then Annual International Symposium-.
623-634.
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Khan, S., Alameldeen, A. R., Wilkerson, C., Mutlu, O., & Jimenez, D. A.
(2014).
Improving Cache Performance Using Read-Write Partitioning. Proceedings - International Symposium on High-Performance Computer Architecture.
452-463.
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Jimenez, D. A.
(2014).
Improving cache performance by exploiting read-write disparity
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Jimnez, D. A.
(2013).
Insertion and promotion for tree-based PseudoLRU last-level caches. 284-296.
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Khan, S. M., Alameldeen, A. R., Wilkerson, C., Kulkarni, J., & Jimnez, D. A.
(2013).
Improving Multi-Core Performance Using Mixed-Cell Cache Architecture. Proceedings - International Symposium on High-Performance Computer Architecture.
119-130.
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Wang, Z., Khan, S. M., & Jimnez, D. A.
(2012).
Rank idle time prediction driven last-level cache writeback. 21-29.
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Khan, S. M., Wang, Z., & Jimnez, D. A.
(2012).
Decoupled Dynamic Cache Segmentation. Proceedings - International Symposium on High-Performance Computer Architecture.
1-12.
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Wang, Z., Khan, S. M., & Jimenez, D. A.
(2012).
Improving Writeback Efficiency with Decoupled Last-Write Prediction. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
309-320.
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Tian, Y., & Jimnez, D. A.
(2011).
Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
209-209.
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Kim, H., Ghoshal, P., Grot, B., Gratz, P. V., & Jimnez, D. A.
(2011).
Reducing Network-on-Chip energy consumption through spatial locality speculation. 233-240.
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Jimnez, D. A.
(2011).
An Optimized Scaled Neural Branch Predictor. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
113-118.
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Khan, S., & Jimnez, D. A.
(2011).
Decoupled Cache Segmentation: Mutable Policy with Automated Bypass. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
212-212.
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Wang, Z., & Jimnez, D. A.
(2011).
Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
210-210.
-
Wang, Z., & Jimnez, D. A.
(2011).
Program Interferometry. 172-175.
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Wang, Z., & Jimnez, D. A.
(2011).
Program Interferometry. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
185-186.
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Jimenez, D. A.
(2011).
Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy
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Khan, S. M., Jimnez, D. A., Burger, D., & Falsafi, B.
(2010).
Using dead blocks as a virtual victim cache. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
489-500.
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Jimenez, D. A.
(2010).
Dead block replacement and bypass with a sampling predictor
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Khan, S., & Jimnez, D. A.
(2010).
Insertion Policy Selection Using Decision Tree Analysis. 106-111.
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Khan, S., Tian, Y., & Jimnez, D. A.
(2010).
Sampling Dead Block Prediction for Last-Level Caches. Micro -Annual Workshop then Annual International Symposium-.
175-186.
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Rahman, S., Wang, Z., & Jimnez, D. A.
(2009).
Studying microarchitectural structures with object code reordering. 7-16.
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Hu, C., Jimnez, D. A., & Kremer, U.
(2009).
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization. 85-104.
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Jimnez, D. A.
(2009).
Composite Confidence Estimators for Enhanced Speculation Control. Proceedings / Symposium on Computer Architecture and High Performance Computing. Symposium on Computer Architecture and High Performance Computing.
161-168.
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St. Amant, R., Jimenez, D. A., & Burger, D.
(2009).
Mixed-Signal Approximate Computation: A Neural Predictor Case Study. IEEE Micro.
104-115.
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Perics, M., Cristal, A., Gonzlez, R., Jimnez, D. A., & Valero, M.
(2008).
Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. 56-67.
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Perics, M., Cristal, A., Cazorla, F. J., Gonzlez, R., Veidenbaum, A., Jimnez, D. A., & Valero, M.
(2008).
A Two-Level Load/Store Queue Based on Execution Locality. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
25-36.
-
Amant, R., Jimnez, D. A., & Burger, D.
(2008).
Low-Power. High-Performance Analog Neural Branch Prediction. Micro -Annual Workshop then Annual International Symposium-.
447-458.
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Perics, M., Cristal, A., Cazorla, F. J., Gonzlez, R., Jimnez, D. A., & Valero, M.
(2007).
A flexible heterogeneous multi-core architecture. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
13-24.
-
Hu, C., Jimnez, D. A., & Kremer, U.
(2007).
Efficient Program Power Behavior Characterization. Lecture Notes in Computer Science.
183-197.
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Perics, M., Cristal, A., Cazorla, F. J., Gonalez, R., Jimnez, D. A., & Valero, M.
(2007).
A Flexible Heterogeneous Multi-Core Architecture. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT.
13-24.
-
Jimenez, D. A., & Loh, G. H.
(2006).
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors* *A subset of the ideas presented in this paper appeared in an earlier workshop with unpublished proceedings. Proceedings / Symposium on Computer Architecture and High Performance Computing. Symposium on Computer Architecture and High Performance Computing.
55-62.
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Jimenez, D. A.
(2006).
Infrequent basic block-based program phase classification and power behavior characterization
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Perics, M., Cristal, A., Gonzlez, R., Jimnez, D. A., & Valero, M.
(2006).
A Decoupled KILO-Instruction Processor. Proceedings - International Symposium on High-Performance Computer Architecture.
52-63.
-
Jimnez, D. A.
(2005).
Code placement for improving dynamic branch prediction accuracy. 107-116.
-
Jimenez, D. A.
(2005).
Reducing the power and complexity of path-based neural branch prediction
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Perics, M., Cristal, A., Gonzlez, R., Jimenez, D. A., & Valero, M.
(2005).
Chained In-Order/Out-of-Order DoubleCore Architecture. Proceedings / Symposium on Computer Architecture and High Performance Computing. Symposium on Computer Architecture and High Performance Computing.
209-216.
-
Jimnez, D. A.
(2005).
Piecewise Linear Branch Prediction. Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture.
382-393.
-
Chunling Hu, .., Jimenez, D. A., & Kremer, U.
(2005).
Toward an Evaluation Infrastructure for Power and Energy Optimizations. 230b-230b.
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Batchu, R. V., & Jimenez, D. A.
(2004).
Exploiting Procedure Level Locality to Reduce Instruction Cache Misses. 75-84.
-
Jimnez, D. A.
(2003).
Fast Path-Based Neural Branch Prediction. Micro -Annual Workshop then Annual International Symposium-.
243-252.
-
Jimnez, D. A.
(2003).
Reconsidering Complex Branch Predictors. Proceedings - International Symposium on High-Performance Computer Architecture.
43-52.
-
Jimenez, D. A.
(2001).
Branch Path Re-Aliasing
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Jimnez, D. A., & Lin, C.
(2001).
Dynamic Branch Prediction with Perceptrons. 197-206.
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Jimnez, D. A., & Lin, C.
(2001).
Perceptron Learning for Predicting the Behavior of Conditional Branches. 2122-2127.
-
Jimnez, D. A., Keckler, S. W., & Lin, C.
(2000).
The impact of delay on the design of branch predictors. 67-76.
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Jimenez, D. A., Keckler, S. W., & Lin, C.
(2000).
The impact of delay on the design of branch predictors. Micro -Annual Workshop then Annual International Symposium-.
67-76.
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Jimenez, D., & Walsh, N.
(1998).
Dynamically weighted ensemble neural networks for classification. 753-756.
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Jimenez, D., Darm, T., Rogers, B., & Walsh, N.
(1997).
Locating anatomical landmarks for prosthetics design using ensemble neural networks. IEEE International Conference on Neural Networks - Conference Proceedings.
81-85 vol.1-85.
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Vavouliotis, G., Chacon, G., Alvarez, L., Gratz, P. V., Jimenez, D. A., & Casas, M.
(2022).
Page Size Aware Cache Prefetching. Micro -Annual Workshop then Annual International Symposium-.
956-974.
-
institutional repository document
-
Gober, N., Chacon, G., Wang, L., Gratz, P. V., Jimenez, D. A., Teran, E., Pugsley, S., & Kim, J.
(2022).
The Championship Simulator: Architectural Simulation for Education and Competition
-
Gober, N., Chacon, G., Wang, L., Gratz, P. V., Jimenez, D. A., Teran, E., Pugsley, S., & Kim, J.
(2022).
The Championship Simulator: Architectural Simulation for Education and Competition
Research
principal investigator on
- FoMR: Adaptive Branch Prediction awarded by National Science Foundation - (Arlington, Virginia, United States) 2019 - 2022
- EAGER: Detecting and Avoiding Side-Channel Attacks with Security Conscious Prediction awarded by National Science Foundation - (Arlington, Virginia, United States) 2019 - 2021
- EAGER: Deep Learning for Microarchitectural Prediction awarded by National Science Foundation - (Arlington, Virginia, United States) 2016 - 2019
- SHF:CSR:Small:Improving Processor Efficiency with Prediction awarded by National Science Foundation - (Arlington, Virginia, United States) 2013 - 2017
Teaching
teaching activities
- CSCE312 Computer Organization Instructor
- CSCE481 Seminar Instructor
- CSCE605 Compiler Design Instructor
- CSCE614 Computer Architecture Instructor
- CSCE684 Professional Internship Instructor
- CSCE684 Professional Internship: In-ab Instructor
- CSCE685 Directed Studies Instructor
- CSCE689 Sptp:microarch Prediction Instructor
- CSCE691 Research Instructor
- CSCE691 Research Instructor
Works By Students
chaired theses and dissertations
-
Backes Drault, Luna B (2017-08). Evaluation of Cache Inclusion Policies in Cache Management.
-
Jindal, Sangam (2018-07). Exploring Alternate Cache Indexing Techniques.
-
Jindal, Sangam (2018-07). Exploring Alternate Cache Indexing Techniques.
-
Teran, Elvira (2017-07). Principled Approaches to Last-Level Cache Management.
-
Tian, Yingying (2015-05). Reducing Waste in Memory Hierarchies.
-
Wang, Zhe (2014-07). Improving Processor Design by Exploiting Performance Variance.
Background
education and training
- Ph.D. in Computer Sciences, The University of Texas at Austin - (Austin, Texas, United States) 2002
- M.S. in Computer Science, The University of Texas at San Antonio - (San Antonio, Texas, United States) 1994
- B.S. in Computer Science and Systems Design, The University of Texas at San Antonio - (San Antonio, Texas, United States) 1992
awards and honors
- Faculty Early Career Development (CAREER) Program, conferred by National Science Foundation - (Arlington, Virginia, United States), 2013
- Distinguished Scientist, conferred by Association for Computing Machinery - (New York, New York, United States), 2012
- ACM Senior Member, conferred by Association for Computing Machinery - (New York, New York, United States), 2008
- Faculty Early Career Development (CAREER) Program, conferred by National Science Foundation - (Arlington, Virginia, United States), 2008
- Faculty Early Career Development (CAREER) Program, conferred by National Science Foundation - (Arlington, Virginia, United States), 2006
Contact
first name
- Daniel
has last name
- Jimenez
mailing address
-
Texas A&M University
Computer Science & Engineering
3112 TAMU
College Station, TX 77843-3112
USA
Other
In the News
- Daniel A. Jiménez Selected to Receive the IEEE Computer Society 2021 B. Ramakrishna Rau Award News Release
- Jiménez appointed interim chair of the Institute of Electrical and Electronics Engineers Computer Society Technical Committee on Computer Architecture News Release
- Jiménez elevated to Institute of Electrical and Electronics Engineers Fellow News Release
- Jiménez honored as 2017 MICRO Hall of Fame inductee News Release
- Jiménez in HPCA Hall of Fame News Release
- Jiménez inducted into International Symposium on Computer Architecture Hall of Fame News Release
- Jiménez receives High-Performance Computer Architecture Test of Time Award News Release
- Jiménez serves as program chair of HPCA 2017 News Release
- Jiménez to help determine top computer architecture papers for publication News Release
- djimenez@tamu.edu