Microprocessors run programs by executing instructions in an assembly-line fashion. The first step decides which instruction to work on next. When a decision-making branch instruction is reached, the processor can''t get the next instruction until the decision is made several steps later. To avoid delays, processors predict where the next instruction will come from. This project investigates ways of improving the accuracy of this and related predictions by adapting the predictor to changing conditions during program execution. Successful outcomes of this project will improve efficiency for mobile phones, desktop and laptop computers, and datacenters. The project will recruit graduate students from under-represented groups and contribute to classroom teaching.The project focuses on microarchitectural predictors driven by machine learning. These predictors use a large number of input features. Currently, features are fixed at design time to cover a wide range of possible program behaviors. The project explores how to adaptively learn features for the current workload. This adaptation will improve accuracy while reducing hardware overhead by using fewer features. This approach applies to several kinds of predictors including conditional and indirect branch prediction, cache reuse prediction, prefetch filtering, replacement in the branch target buffer, instruction cache, and translation look-aside buffers.This award reflects NSF''s statutory mission and has been deemed worthy of support through evaluation using the Foundation''s intellectual merit and broader impacts review criteria.
