SHF:CSR:Small:Improving Processor Efficiency with Prediction
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For several decades, computers have been getting faster. Much of this improvement in performance is due to Moore''s Law, i.e., the rapid growth in the number of devices that can be integrated into a single microchip. However, techniques that exploit the growing resources provided by Moore''s Law are often inefficient and wasteful. This project takes a hard look at techniques used to improve performance, showing how resource-hungry techniques can be made less wasteful. The improved structures use techniques borrowed from other areas of Computer Science to predict the near-term resource usage of the computer to do a better job of allocating those resources. These prediction techniques result in a system that is both more power efficient and better performing.Improvements in power efficiency and performance have a wide-ranging impact, from improving battery life in mobile devices to reducing energy costs and environmental impact of data centers. The project will involve university students in research, helping to train the next generation of technology workers and educators.This project applies microarchitectural prediction techniques to recover wasted resources and thus improve the efficiency of microprocessors. The project explores the following opportunities for reducing waste with prediction: 1) applying highly accurate branch prediction techniques to other domains such as caches, 2) using mixed analog/digital circuit implementations to improve prediction accuracy while reducing waste in the predictor itself, and 3) developing a set of new confidence estimation techniques and considering their use in a variety of microarchitectural optimizations.