Power Gating with Block Migration in Chip-Multiprocessor Last-Level Caches Conference Paper uri icon

abstract

  • We propose a novel technique to significantly reduce the leakage energy of last level caches while mitigating any significant performance impact. In general, cache blocks are not ordered by their temporal locality within the sets; hence, simply power gating off a partition of the cache, as done in previous studies, may lead to considerable performance degradation. We propose a solution that migrates the high temporal locality blocks to facilitate power gating, where blocks likely to be used in the future are migrated from the partition being shutdown to the live partition at a negligible performance impact and hardware overhead. Our detailed simulations show energy savings of 66% at low performance degradation of 2.16%. 2013 IEEE.

name of conference

  • 2013 IEEE 31st International Conference on Computer Design (ICCD)

published proceedings

  • 2013 IEEE 31ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)

author list (cited authors)

  • Kadjo, D., Kim, H., Gratz, P., Hu, J., & Ayoub, R.

citation count

  • 12

complete list of authors

  • Kadjo, David||Kim, Hyungjun||Gratz, Paul||Hu, Jiang||Ayoub, Raid

publication date

  • October 2013