A massively scaleable decoder architecture for low-density parity-check codes Conference Paper uri icon

abstract

  • A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this throughput is achieved without significant bit-error performance degradation.

published proceedings

  • PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II

author list (cited authors)

  • Selvarathinam, A., Choi, G., Narayanan, K., Prabhakar, A., & Kim, E.

complete list of authors

  • Selvarathinam, A||Choi, G||Narayanan, K||Prabhakar, A||Kim, E

publication date

  • January 1, 2003 11:11 AM