A massively scaleable decoder architecture for low-density parity-check codes
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A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this throughput is achieved without significant bit-error performance degradation.
author list (cited authors)
Selvarathinam, A., Choi, G., Narayanan, K., Prabhakar, A., & Kim, E.