A massively scaleable decoder architecture for low-density parity-check codes Conference Paper

abstract

• A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this throughput is achieved without significant bit-error performance degradation.

authors

• Choi, Gwan
• Narayanan, Krishna

published proceedings

• PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II

author list (cited authors)

• Selvarathinam, A., Choi, G., Narayanan, K., Prabhakar, A., & Kim, E.

complete list of authors

• Selvarathinam, A||Choi, G||Narayanan, K||Prabhakar, A||Kim, E

publication date

• July 2003

published in

• IEEE International Symposium on Circuits and Systems  Journal

keywords

• Ber/fer
• Hardware Scaling
• Ldpc Decoder
• Parallel Architecture
• Vlsi

International Standard Book Number (ISBN) 10

• 0-7803-7761-3

start page

• 61

end page

• 64

volume

• 2