LDPC code for reduced routing decoder Conference Paper uri icon

abstract

  • A design approach that reduces the routing complexity in a VLSI implementation of Low-Density Parity-Check (LDPC) decoder is presented. An LDPC code is a linear-block code for forward error correction, attributed by a sparse parity-check matrix. Iterative decoding of this code is shown to yield Bit Error Rate (BER) performance approaching Shannon Limit. However, implementation of decoder for this code is difficult due to the routing requirements of its massive number of data-flow structures in decoding logic. We present a routing approach for a parallel LDPC decoder implementation by 1) analyzing the physical routability limitations and 2) designing the code parameters to limit the interconnect lengths to a bounded region. The approach does not compromise the BER performance, and yet achieves a much higher throughput resulting from significantly reduced wires lengths. 2005 IEEE.

name of conference

  • 2005 Asia-Pacific Conference on Communications

published proceedings

  • 2005 ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS (APCC), VOLS 1& 2

altmetric score

  • 3

author list (cited authors)

  • Kim, E., & Choi, G. S.

citation count

  • 0

complete list of authors

  • Kim, E||Choi, GS

publication date

  • January 2005