VLSI implementation of a staggered sphere decoder design for MIMO detection Conference Paper uri icon


  • MIMO is a key technology for future high speed wireless communication applications. Present MIMO systems are constrained by the lack of efficient detection algorithms/hardware architectures. In this paper we present a novel algorithm/architecture which takes a hybrid approach toward MIMO detection in the sense that it simultaneously searches along the depth and breadth of the tree. We have implemented our architecture using an ASIC design flow in a 100nm process technology. Our implementation results are compared with fully serial, fully parallel, and sequential architectures, We refer to the proposed algorithm as Staggered Sphere Decoding with Ordering (SSDO). SSBO is an excellent match for high throughput MIMO-OFDM systems like 802.11n etc. ASIC estimates (using a 100nm technology) indicate that SSDO achieves a guaranteed minimum throughput of 287 Mbps, with an area utilization of 2070 2. Our approach achieves significantly higher throughput than the serial and sequential approaches, and half the throughput of the parallel approach (using a fifth of its area). The throughput per unit power and throughput per unit area are significantly improved over the parallel, serial and sequential approaches.

published proceedings

  • 45th Annual Allerton Conference on Communication, Control, and Computing 2007

author list (cited authors)

  • Bhagawat, P., Ekambavanan, S., Das, S., Choi, G., & Khatri, S. P.

complete list of authors

  • Bhagawat, P||Ekambavanan, S||Das, S||Choi, G||Khatri, SP

publication date

  • January 2007