Signal Reconstruction Processor Design For Compressive Sensing Conference Paper

abstract

• This paper presents a very-large-scale integration (VLSI) design to reconstruct compressively sensed data. The proposed digital design recovers signal compressed by specific analog-to-digital converter (ADC). Our design is based on a modified iterative hard threshold (IHT) reconstruction algorithm to adapt unknown and varying degree of sparsity of the signal. The algorithm is composed empirically and implemented in a hardware-friendly fashion. The reconstruction fidelity using fixed-point hardware model is analyzed. The design is synthesized using Synopsys Design Compiler with TSMC 45nm standard cell library. The post-synthesis implementation consumes 165 mW and is able to reconstruct data with information sparsity of 4%, at equivalent sampling rate of 1 gigasample-per-second (GSPS). 2014 IEEE.

name of conference

• 2014 IEEE International Symposium on Circuits and Systems (ISCAS)

authors

• Choi, Gwan

published proceedings

• 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)

author list (cited authors)

• Xu, J., Rohani, E., Rahman, M., & Choi, G.

citation count

• 2

complete list of authors

• Xu, Jingwei||Rohani, Ehsan||Rahman, Mehnaz||Choi, Gwan

publication date

• January 2014

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems  Journal

Digital Object Identifier (DOI)

• 10.1109/iscas.2014.6865690

International Standard Book Number (ISBN) 13

• 9781479934324

start page

• 2539

end page

• 2542

URL

• http://dx.doi.org/10.1109/iscas.2014.6865690