Signal Reconstruction Processor Design for Compressive Sensing
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This paper presents a very-large-scale integration (VLSI) design to reconstruct compressively sensed data. The proposed digital design recovers signal compressed by specific analog-to-digital converter (ADC). Our design is based on a modified iterative hard threshold (IHT) reconstruction algorithm to adapt unknown and varying degree of sparsity of the signal. The algorithm is composed empirically and implemented in a hardware-friendly fashion. The reconstruction fidelity using fixed-point hardware model is analyzed. The design is synthesized using Synopsys Design Compiler with TSMC 45nm standard cell library. The post-synthesis implementation consumes 165 mW and is able to reconstruct data with information sparsity of 4%, at equivalent sampling rate of 1 gigasample-per-second (GSPS). © 2014 IEEE.
author list (cited authors)
Xu, J., Rohani, E., Rahman, M., & Choi, G.