Asynchronous Design for Precision-Scaleable Energy-Efficient LDPC Decoder Conference Paper

abstract

• 2014 IEEE. This paper presents a low-density parity-check (LDPC) decoder design that uses scalable-precision calculation (SPC) and asynchronous circuit techniques to reduce power consumption. The decoder configures the computation precision to minimize circuit-level switching necessary for given target biterror rate (FER). The asynchronous circuit approach guarantees the completion of each compute-and-forward phase at necessary voltage levels. The voltage level is scheduled to ensure completion of minimum necessary decoding iterations. The proposed scheme is studied for the specific application of IEEE 802.16e to reduce the power consumption at a given target FER. The proposed design is evaluated on Nangate 45nm library. The results show that the proposed asynchronous design results in 51% reduction in terms of power consumption compared with full-precision decoding mode.

name of conference

• 2014 48th Asilomar Conference on Signals, Systems and Computers

authors

• Choi, Gwan

published proceedings

• CONFERENCE RECORD OF THE 2014 FORTY-EIGHTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS

author list (cited authors)

• Xu, J., Che, T., Rohani, E., & Choi, G.

citation count

• 0

complete list of authors

• Xu, Jingwei||Che, Tiben||Rohani, Ehsan||Choi, Gwan

publication date

• January 2014

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers  Journal

keywords

• Asynchronous Circuits
• Ldpc
• Low-power Design
• Precision-scalable
• Voltage Scaling Design

Digital Object Identifier (DOI)

• 10.1109/acssc.2014.7094413

International Standard Book Number (ISBN) 13

• 9781479982974

start page

• 136

end page

• 140

volume

• 2015-April

URL

• http://dx.doi.org/10.1109/acssc.2014.7094413