A fast and accurate gate-level transient fault simulation environment Conference Paper uri icon

abstract

  • Mixed analog and digital mode simulators have been available for accurate transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. The simulation environment uses a timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses high level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The simulation environment is demonstrated on ISCAS-89 sequential benchmark circuits.

name of conference

  • FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing

published proceedings

  • FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing

author list (cited authors)

  • Cha, H., Rudnick, E. M., Choi, G. S., Patel, J. H., & Iyer, R. K.

citation count

  • 31

complete list of authors

  • Cha, H||Rudnick, EM||Choi, GS||Patel, JH||Iyer, RK

publication date

  • January 1993

published in