Multi-rate layered decoder architecture for block LDPC codes of the IEEE 802.11n wireless standard
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We present a new multi-rate architecture for decoding block LDPC codes in IEEE 802.11n standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. Techniques of data-forwarding and out-of-order processing are used to deal with the irregularity of the codes. The decoder has the following advantages when compared to recent state-of-the-art architectures: 55% savings in memory, reduction of routers by 50% and increase of throughput by 2x. © 2007 IEEE.
author list (cited authors)
Gunnam, K., Choi, G., Wang, W., & Yeary, M.