Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard Conference Paper

abstract

• We present a new multi-rate architecture for decoding block LDPC codes in IEEE 802.11n standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. Techniques of data-forwarding and out-of-order processing are used to deal with the irregularity of the codes. The decoder has the following advantages when compared to recent state-of-the-art architectures: 55% savings in memory, reduction of routers by 50% and increase of throughput by 2x. 2007 IEEE.

name of conference

• 2007 IEEE International Symposium on Circuits and Systems

authors

• Choi, Gwan

published proceedings

• 2005 IEEE International Symposium on Circuits and Systems (ISCAS)

author list (cited authors)

• Gunnam, K., Choi, G., Wang, W., & Yeary, M.

citation count

• 44

complete list of authors

• Gunnam, K||Choi, Gwan||Wang, Weihuang||Yeary, M

publication date

• January 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems  Journal

Digital Object Identifier (DOI)

• 10.1109/iscas.2007.378835

start page

• 1645

end page

• 1648

URL

• http://dx.doi.org/10.1109/iscas.2007.378835