Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation Conference Paper uri icon

abstract

  • The implementation complexity of the decoder for Low-density parity-check Codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC Decoder architectures that reduce the need of message passing memory by 80% (for standard message passing)-55%(for layered decoding) and the router requirements by more than 50%. These novel architectures are based on scheduling of computation that results in "on the fly computation" of variable node and check node reliability messages. These architectures are targeted for quasi-cyclic LDPC codes such as array LDPC codes (regular QC-LDPC) and Block LDPC codes (irregular QC-LDPC). FPGA and ASIC implementation results show substantial gains when compared to the existing work in the literature.

name of conference

  • 2006 Fortieth Asilomar Conference on Signals, Systems and Computers

published proceedings

  • 2006 Fortieth Asilomar Conference on Signals, Systems and Computers

author list (cited authors)

  • Gunnam, K. K., Choi, G. S., Wang, W., Kim, E., & Yeary, M. B.

citation count

  • 17

complete list of authors

  • Gunnam, Kiran K||Choi, Gwan S||Wang, Weihuang||Kim, Euncheol||Yeary, Mark B

publication date

  • October 2006

publisher