Decoding of quasi-cyclic LDPC codes using an on-the-fly computation
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abstract
The implementation complexity of the decoder for Low-density parity-check Codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC Decoder architectures that reduce the need of message passing memory by 80% (for standard message passing)-55%(for layered decoding) and the router requirements by more than 50%. These novel architectures are based on scheduling of computation that results in "on the fly computation" of variable node and check node reliability messages. These architectures are targeted for quasi-cyclic LDPC codes such as array LDPC codes (regular QC-LDPC) and Block LDPC codes (irregular QC-LDPC). FPGA and ASIC implementation results show substantial gains when compared to the existing work in the literature.
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2006 Fortieth Asilomar Conference on Signals, Systems and Computers