Decoding of Quasi-Cyclic LDPC Codes Using an On-the-Fly Computation Conference Paper uri icon


  • The implementation complexity of the decoder for Low-density parity-check Codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC Decoder architectures that reduce the need of message passing memory by 80% (for standard message passing)-55%(for layered decoding) and the router requirements by more than 50%. These novel architectures are based on scheduling of computation that results in "on the fly computation" of variable node and check node reliability messages. These architectures are targeted for quasi-cyclic LDPC codes such as array LDPC codes (regular QC-LDPC) and Block LDPC codes (irregular QC-LDPC). FPGA and ASIC implementation results show substantial gains when compared to the existing work in the literature.

author list (cited authors)

  • Gunnam, K. K., Choi, G. S., Wang, W., Kim, E., & Yeary, M. B.

publication date

  • January 1, 2006 11:11 AM