A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes Conference Paper uri icon

abstract

  • The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data-reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction of logic and interconnects requirements of the decoder when compared to the state-of-the-art LDPC decoders. The ASIC implementation of the proposed fully parallel architecture achieves throughput of 4.6 Gbps (for a maximum of 15 iterations). The chip size is 2.3 mm x 2.3 mm in 0.13 micron technology. 2007 IEEE.

name of conference

  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

published proceedings

  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

author list (cited authors)

  • Gunnam, K., Choi, G., & Yeary, M.

citation count

  • 28

complete list of authors

  • Gunnam, Kiran||Choi, Gwan||Yeary, Mark

publication date

  • January 2007

publisher