A novel hardware hash unit design for modern microprocessors Conference Paper uri icon


  • 2016 IEEE. Historically, microprocessor instructions were designed in order to obtain high performance on integer and floating point computations. Today's applications, however, demand high performance for cloud computing, web-based search engines, network applications, and social media tasks. Such software applications involve an extensive use of hashing in their computation. Hashing can reduce the complexity of search and lookup from O(n) to O(n/k), where k bins are used. In modern microprocessors hashing is done in software. In this paper, we propose a novel hardware hash unit design for use in modern microprocessors. We present the design of the Hash Unit (HU) at the micro-architecture level. We simulate the new HU to compare its performance with a software-based hash implementation. We demonstrate a significant speed-up (up to 12) for the HU. Furthermore, the performance scales elegantly with increasing database size and application diversity, without increasing the hardware cost.

name of conference

  • 2016 IEEE 34th International Conference on Computer Design (ICCD)

published proceedings

  • 2016 IEEE 34th International Conference on Computer Design (ICCD)

author list (cited authors)

  • Fairouz, A., Abusultan, M., & Khatri, S. P.

citation count

  • 3

complete list of authors

  • Fairouz, Abbas||Abusultan, Monther||Khatri, Sunil P

publication date

  • October 2016