On-chip bidirectional wiring for heavily pipelined systems using network coding Conference Paper uri icon

abstract

  • In this paper, we describe a low-area, reducedpower on-chip point-to-point bidirectional communication scheme for heavily pipelined systems. When data needs to be transmitted bidirectionally between two on-chip locations, the traditional approach resorts to either using two unidirectional wires, or to using a single wire (with a unidirectional transfer at any given time instant). In contrast, our bidirectional communication scheme allows data to be transmitted simultaneously between two on-chip locations, with a single wire performing the bidirectional data transfer. Our approach borrows ideas from the emerging area of network coding (in the field of communication). By utilizing coding units (which also serve the purpose of buffering the signals) along the wire between the two endpoints, we are able to achieve the same throughput as a traditional approach, while reducing the total area utilization by about 49.8% (thereby reducing routing congestion), and the total power consumption by about 11.5%. The area and power results include the contribution of routing wires, coding units, drivers, the clock distribution network and the required reset wire. Our bidirectional communication approach is ideally suited for heavily pipelined data intensive systems. 2009 IEEE.

name of conference

  • 2009 IEEE International Conference on Computer Design (ICCD 2009)

published proceedings

  • 2009 IEEE International Conference on Computer Design

author list (cited authors)

  • Bollapalli, K. C., Garg, R., Gulati, K., & Khatri, S. P.

citation count

  • 2

complete list of authors

  • Bollapalli, Kalyana C||Garg, Rajesh||Gulati, Kanupriya||Khatri, Sunil P

publication date

  • October 2009

publisher