Performance Driven Global Routing Through Gradual Refinement Academic Article

abstract

• We propose a method for VLSI interconnect global routing that can optimize routing congestion, delay and number of bends, which are often competing objectives. Routing flexibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints. The wire routes are determined through gradual refinement according to probabilistic estimation on congestions so that the congestion is minimized while the number of bends on wires are limited. The experiments on both random generated circuits and benchmark circuits confirm the effectiveness of this method.

authors

• Hu, Jiang

published proceedings

• Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001

author list (cited authors)

• Hu, J., & Sapatnekar, S. S.

citation count

• 1

complete list of authors

• Hu, Jiang||Sapatnekar, Sachin S

publication date

• January 2001

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Conference on Computer Design - VLSI in Computers and Processors  Journal

Digital Object Identifier (DOI)

• 10.1109/iccd.2001.955070

start page

• 481

end page

• 483

URL

• http://dx.doi.org/10.1109/iccd.2001.955070