Exploring Static and Dynamic Flash-based FPGA Design Topologies
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abstract
2016 IEEE. Field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, SRAM-based FPGAs suffer from high power consumption, prolonged boot delays (due to the volatility of the configuration bits), and a significant area overhead (due to the use of 5T SRAM cells for the configuration bits). Floating gate (flash) based FPGAs can avert these problems. This paper presents a study of flash-based FPGA designs (both static and dynamic), and presents the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished. Our delay and power estimates are derived from circuit level simulations. Our proposed static flash-based LUT structure yields 10% faster operation, 12% lower dynamic power dissipation, 21% lower energy consumption and 29% lower static power dissipation compared to a traditional SRAM-based LUT. We also show that, for high performance applications, a dynamic flash-based LUT can achieve further performance improvements (32% lower delay) with higher energy consumption (37% higher) compared to an SRAM-based LUT. We also show that a flash-based interconnect structure provides 89% lower delay and 71% lower overall power consumption compared to the traditional interconnect structure used in SRAM-based FPGAs.
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2016 IEEE 34th International Conference on Computer Design (ICCD)
