A Structured ASIC Design Approach Using Pass Transistor Logic Conference Paper uri icon


  • In this paper, we describe a structured ASIC design methodology which utilizes a regular, pre-fabricated array of pass transistor logic based if-then-else (ITE) cells as the building block for the circuit. Given a logic netlist, we first construct Reduced Order Binary Decision Diagrams (ROBDDs) for the circuit in a partitioned manner, thereby allowing the approach to handle large designs. We place the ITE cells corresponding to the ROBDD nodes in a manner that minimizes crossings in the ROBDD graph. Our placement also effectively 'folds' the ITE cells of different variables into a single row, so as to obtain a layout with a more uniform distribution of ITE cells along each physical row of ITE cells. The design methodology has been demonstrated to implement sequential as well as combinational designs, by customizing the lowest 4 METAL layers along with their associated VIA layers. A low area and delay overhead is achieved, in comparison with an ASIC approach. In particular, the average delay (area) overhead is 1.5 (3.41) for combinational designs and 2 (6) for sequential designs. 2007 IEEE.

name of conference

  • 2007 IEEE International Symposium on Circuits and Systems

published proceedings

  • 2007 IEEE International Symposium on Circuits and Systems

author list (cited authors)

  • Gulati, K., Jayakumar, N., & Khatri, S. P.

citation count

  • 8

complete list of authors

  • Gulati, Kanupriya||Jayakumar, Nikhil||Khatri, Sunil P

publication date

  • May 2007