A PLA based asynchronous micropipelining approach for subthreshold circuit design Conference Paper uri icon


  • Power consumption is a dominant issue in contemporary circuit design. Sub-threshold circuit design is an appealing means to dramatically reduce this power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs. We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7x, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4x, compared to a traditional network of PLA design. Our approach is quite general, and can be applied to traditional circuits as well. Copyright 2006 ACM.

name of conference

  • Proceedings of the 43rd annual conference on Design automation - DAC '06

published proceedings

  • Proceedings of the 43rd annual conference on Design automation - DAC '06

author list (cited authors)

  • Jayakumar, N., Garg, R., Gamache, B., & Khatri, S. P.

citation count

  • 12

complete list of authors

  • Jayakumar, Nikhil||Garg, Rajesh||Gamache, Bruce||Khatri, Sunil P

publication date

  • January 2006