Exploiting Crosstalk to Speed up On-chip Buses
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In modern VLSI processes, the cross-coupling capacitance between adjacent neighboring wires on the same metal layer is a very large fraction of the total wire capacitance. This leads to problems of delay variation due to crosstalk and reduced noise immunity, arguably one of the biggest obstacles in the design of ICs in recent times. This problem is particularly severe in long on-chip buses, since bus signals are routed at minimum pitch for long distances. In this work, we propose to solve this problem by the use of crosstalk canceling CODECs. We only utilize memoryless CODECs, to reduce the logical complexity and enhance the robustness of our techniques. Bus data patterns can be classified (as 4 C, 3 C, 2 C, 1 C or 0 C patterns) based on the maximum amount of crosstalk that they can exhibit. Crosstalk avoidance CODECs which eliminate 4 C and 3 C patterns have been reported. In this paper, we describe crosstalk avoidance techniques which eliminate 2 C and 1 C patterns. We describe an analytical methodology to accurately characterize the bus area overhead 2 C pattern CODECs. Using these results, we characterize the area overhead versus crosstalk immunity achieved. A similar exercise is performed for 1 C patterns. Our experimental results show that by using 2 C crosstalk canceling techniques, buses can be sped up by up to a factor of 6 with an area overhead of about 200%, and that 1 C techniques are not very robust.
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Proceedings Design, Automation and Test in Europe Conference and Exhibition
