Improving FPGA routability using network coding
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With current technology trends, FPGA routing is an important problem, since routing in FPGAs contributes significantly to delay and resource utilization, as compared to the logic portion of FPGAs. In this paper we improve the FPGA routing characteristics by applying the technique of network coding. This relatively new technique was developed in the context of communication networks, and proven to improve network throughput, reliability, etc. To the best of our knowledge, this paper is the first to apply network coding to improve FPGA routing. Our preliminary results are implemented in the VPR 4.30 tool suite. We demonstrate (on average) a 14% reduction in worst case delay, a 3% reduction in wirelength and a healthy reduction in the routing track count on several MCNC benchmark circuits, over the current best known results. By using carefully generated cost models for applying the technique of network coding, we show that this routability improvement is accompanied by a zero percent CLB utilization overhead and < 0.5% runtime penalty. Our approach is orthogonal to existing routing algorithms, and therefore can be applied in tandem with them. Copyright 2008 ACM.
name of conference
the 18th ACM Great Lakes symposium
Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08
author list (cited authors)
Gulati, K., & Khatri, S. P.
complete list of authors
Gulati, Kanupriya||Khatri, Sunil P