A Ternary-valued, Floating Gate Transistor-based Circuit Design Approach Conference Paper uri icon

abstract

  • 2016 IEEE. This paper presents a method to use floating gate (flash) transistors to implement low power ternary-valued digital circuits targeting handheld and IoT devices. Since the threshold voltage of flash devices can be modified at a fine granularity during programming, our approach has several advantages. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. We present the circuit topology that we use in our flash-based ternary-valued logic digital circuit approach, and, through circuit simulations, show that our approach yields significantly improved power (~11%), energy (~29%) and area (~83%) characteristics while operating at a clock rate that is 36% as compared to a traditional CMOS standard cell based approach, when averaged over 20 designs. Unlike CMOS, our ternary-valued, flash-based implementation provides in-field configuration flexibility.

name of conference

  • 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

published proceedings

  • 2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)

author list (cited authors)

  • Abusultan, M., & Khatri, S. P.

citation count

  • 5

complete list of authors

  • Abusultan, Monther||Khatri, Sunil P

publication date

  • July 2016