An Automated Approach for Minimum Jitter Buffered H-Tree Construction Conference Paper uri icon

abstract

  • In recent fabrication technologies, buffered clock distribution networks have become increasingly popular due to increasing on-chip wiring delays. Traditionally, clock distribution networks has been optimized to minimize end-to-end skew of the distribution network. However, since most ICs have an on-chip PLL, we argue that the design goal of minimizing end-to-end jitter is more relevant. In this paper, we present a dynamic programming based approach to synthesize a minimum cost buffered H-tree clock distribution network. Our cost functions are a weighted sum of power and jitter, and a weighted sum of power and end-to-end delay of the distribution network. Our approach is based on pre-characterizing the delay, jitter and power of buffered segments of different lengths, topologies, buffer sizes and wire-codes. Using this information, a dynamic programming (DP) engine automatically generates the optimal H-tree that minimizes the appropriate cost function. Compared to a manually constructed buffered H-tree network, our approaches are able to reduce both jitter (by as much as 28%, and power by as much as 46%. When optimizing for minimum jitter, the DP engine generates a H-tree with lower jitter than when optimizing for minimum delay, thereby validating our approach, and proving its usefulness. 2011 IEEE.

name of conference

  • 2011 24th International Conference on VLSI Design: concurrently with the 10th International Conference on Embedded Systems Design

published proceedings

  • 2011 24th Internatioal Conference on VLSI Design

author list (cited authors)

  • Mandal, A., Jayakumar, N., Bollapalli, K., Khatri, S. P., & Mahapatra, R. N.

citation count

  • 2

complete list of authors

  • Mandal, A||Jayakumar, N||Bollapalli, K||Khatri, SP||Mahapatra, RN

publication date

  • January 2011

publisher