Design of a Flash-based Circuit for Multi-valued Logic
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abstract
Copyright 2017 ACM. Flash transistors serve as the technology of choice for implementing non-volatile memory. Current flash memory densities are increasing to meet storage demands. One of the key features that has resulted in increasing flash memory densities is the ability to program a flash transistor to have multiple threshold voltages. This feature has recently been exploited to implement ternary-valued logic. However, this implementation exhibited increased delays, due to the lowered VgS values which result from using multiple threshold voltages. In this work, we present a circuit implementation that uses flash transistors to implement multi-valued digital circuits. The flash transistors used in our implementation only need two threshold voltages. As a result they have high Vgs values which improves delays significantly, and have higher write endurance as well. We evaluate our design methodology through circuit simulations, and compare our results to a CMOS standard cell based approach as well as the previously reported implementation of ternary-valued logic using flash transistors. Averaged over 20 designs, we report improvements in delay (23% lower), power (5% lower), energy (26% lower) and physical area (4% lower) compared to a CMOS standard cell based implementation. This is significant since it is hard for a new circuit approach to beat the established standard cell based approach in all the figures of merit (delay, area, power and energy. Compared to the ternary flash-based implementation, we operate at 3.15 x faster than the ternary flash-based designs, while consuming more power and energy. The design approach presented in this paper targets high performance applications, unlike the TLC-based approach which targets low power and low speed applications. Also, the proposed approach scales elegantly to multi-valued logic using more than three values as well.
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Proceedings of the on Great Lakes Symposium on VLSI 2017
