An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification Conference Paper uri icon

abstract

  • Leakage power currently comprises a large fraction of the total power consumption of an IC. Techniques to minimize leakage have been researched widely. In this paper, we present an approach which minimizes leakage by simultaneously modifying the circuit while deriving the input vector that minimizes leakage. In our approach, we selectively modify a gate so that its output (in sleep mode) is in a state which helps minimize the leakage of other gates in its transitive fanout. Gate replacement is performed in a slack-aware manner, to minimize the resulting delay penalty. © 2007 EDAA.

author list (cited authors)

  • Jayakumar, N., & Khatri, S. P.

citation count

  • 12

publication date

  • April 2007

publisher