Toggle Equivalence Preserving (TEP) Logic Optimization Conference Paper uri icon

abstract

  • We describe a procedure (called the TEP procedure) that, given a multi-output circuit M, builds another multi-output circuit M* that is toggle equivalent to M. The TEP procedure can be used in the following two scenarios. First, since for single-output circuits toggle equivalence means functional equivalence, the TEP procedure can be used in "regular" logic synthesis. Second, the TEP procedure enables a powerful synthesis method called LS_TE (Logic Synthesis preserving Toggle Equivalence). Given a circuit N and its partitioning into subcircuits Ni , LS_TE builds an optimized circuit N* by replacing subcircuits Ni with their toggle equivalent counterparts N*i . The replacement of Ni with N*i is done by the TEP procedure. We give results of optimizing single-output circuits by the TEP procedure and some preliminary results of using the TEP procedure in LS_TE. These results show the promise of the TEP procedure and LS_TE. 2007 IEEE.

name of conference

  • 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

published proceedings

  • 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

author list (cited authors)

  • Goldberg, E., Gulati, K., & Khatri, S.

citation count

  • 0

complete list of authors

  • Goldberg, Eugene||Gulati, Kanupriya||Khatri, Sunil

publication date

  • August 2007