Analysis and avoidance of cross-talk in on-chip buses Conference Paper uri icon

abstract

  • 2001 IEEE. We present techniques to analyze and alleviate cross-talk in on-chip buses. With rapidly shrinking process feature sizes, wire delay is becoming a large fraction of the overall delay of a circuit. Additionally, the increasing cross-coupling capacitances between wires on the same metal layer create a situation where the delay of a wire is strongly dependent on the electrical state of its neighboring wires. The delay of a wire can vary widely depending on whether its neighbors perform a like or unlike transition. This effect is acute for long on-chip buses. In this work, we classify cross-talk interactions between the wires of an on-chip bus. We present encoding techniques which can help a designer trade off cross-talk against area overhead. Our experimental results show that the proposed techniques result in reduced delay variation due to cross-talk. As a result, the overall delay of a bus actually decreases even after the use of the encoding scheme.

name of conference

  • HOT 9 Interconnects

published proceedings

  • HOT 9 Interconnects. Symposium on High Performance Interconnects

author list (cited authors)

  • Chunjie Duan, .., Anup Tirumala, .., & Khatri, S. P.

citation count

  • 108

complete list of authors

  • Khatri, SP

publication date

  • January 2001