Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction Academic Article uri icon

abstract

  • Boolean satisfiability (SAT) is a core non polynomial (NP)-complete problem. Several heuristic software and hardware approaches have been proposed to solve this problem. The authors present a hardware solution to the SAT problem. They propose a custom integrated circuit (IC) to implement their approach, in which the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. Further, extracting the minimum unsatisfiable core (i.e. the formula consisting of the smallest set of clauses of the initial formula which is unsatisfiable) is also a computationally hard problem. The proposed hardware approach, in addition to solving SAT, efficiently extracts the minimum unsatisfiable core for any unsatisfiable formula. To the best of the authors' knowledge, this is the first hardware-based solution proposed for extracting the unsatisfiable core. In this approach, clause literals are stored in specially designed clause cells. Clauses are implemented in banks, in a manner that allows clauses of variable width to be accommodated in these banks. To maximise the utilisation of these banks, the authors initially partition the SAT problem. Their solution has significantly larger capacity than existing hardware SAT solvers, and is scalable in the sense that several ICs can be used to simultaneously operate on the same SAT instance. The area, power and performance figures are derived from layout and SPICE (using extracted parasitics) estimates. The approach presented has been functionally validated in Verilog. Preliminary results demonstrate that the approach can accommodate instances with approximately 63K clauses on a single IC of size 1.5cm×1.5cm. This hardware based-SAT solving approach results in over three orders of magnitude speed improvement over Boolean constraint propogation-based software SAT approaches (one to two orders of magnitude over other hardware SAT approaches). The capacity of this approach is significantly higher than most hardware-based approaches. Further, the worst case power consumption was found to be ≤1mW for the implementation. © 2008 The Institution of Engineering and Technology.

author list (cited authors)

  • Gulati, K., Waghmode, M., Khatri, S. P., & Shi, W.

citation count

  • 12

publication date

  • January 2008