HR job title
- Professor
- Contact Info
- 1 979 845 3820
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Shi, Weiping Professor
Positions
My research interests include computer-aided design of Very Large Scale Integration (VLSI) CAD, including physical design, parasitic extraction, fault diagnosis, variational analysis and process synthesis.
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- Works By Students
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Overview
Publications
selected publications
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academic article
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Zhou, Y., Zhang, Y., Sarin, V., Qiu, W., & Shi, W.
(2016).
Macro Model of Advanced Devices for Parasitic Extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
35(10), 1721-1729.
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Li, Z., Zhou, Y. N., & Shi, W.
(2012).
O(mn) Time Algorithm for Optimal Buffer Insertion of Nets with m Sinks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
31(3), 437-441.
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Yi, Y., Wenzel, R., Sarin, V., & Shi, W.
(2009).
Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
28(7), 1106-1110.
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Yi, Y., Wenzel, R., Sarin, V., & Shi, W.
(2009).
Inductance extraction for interconnects in the presence of nonlinear magnetic materials. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
28(1), 1106-1110.
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Liu, Y., Hu, J., & Shi, W.
(2008).
Buffering Interconnect for Multicore Processor Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
27(12), 2183-2196.
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Yi, Y., Li, P., Sarin, V., & Shi, W.
(2008).
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
27(11), 1918-1927.
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Gulati, K., Waghmode, M., Khatri, S. P., & Shi, W.
(2008).
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Computers and Digital Techniques.
2(3), 214-229.
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Hu, S., Alpert, C. J., Hu, J., Karandikar, S. K., Li, Z., Shi, W., & Sze, C. N.
(2007).
Fast algorithms for slew-constrained minimum cost buffering. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
26(11), 2009-2022.
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Sze, C. N., Alpert, C. J., Hu, J., & Shi, W.
(2007).
Path-based buffer insertion. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
26(7), 1346-1355.
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Li, Z., Zhou, Y., & Shi, W.
(2007).
Wire sizing for non-tree topology. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
26(5), 872-880.
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Yan, S., Sarin, V., & Shi, W.
(2006).
Fast 3-D capacitance extraction by inexact factorization and reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
25(10), 2282-2286.
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Li, Z., & Shi, W. P.
(2006).
An O(bn(2)) time algorithm for optimal buffer insertion with b buffer types. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
25(3), 484-489.
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Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W. P.
(2005).
Longest-path selection for delay test under process variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
24(12), 1924-1929.
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Yan, S., Sarin, V., & Shi, W. P.
(2005).
Sparse transformations and preconditioners for 3-D capacitance extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
24(9), 1420-1426.
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Shi, W. P., & Li, Z.
(2005).
A fast algorithm for optimal buffer insertion. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
24(6), 879-891.
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Shi, W., & Su, C.
(2005).
The Rectilinear Steiner Arborescence Problem Is NP-Complete. SIAM Journal on Computing.
35(3), 729-740.
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Shi, W., & Yu, F.
(2004).
A Divide-and-Conquer Algorithm for 3-D Capacitance Extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
23(8), 1157-1163.
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Li, Z., Lu, X., Qiu, W. Q., Shi, W. P., & Walker, D.
(2003).
A circuit level fault model for resistive bridges. ACM Transactions on Design Automation of Electronic Systems.
8(4), 546-559.
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Shi, W., Liu, J., Kakani, N., & Yu, T.
(2002).
A Fast Hierarchical Algorithm for Three-Dimensional Capacitance Extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
21(3), 330-336.
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Shi, W., & West, D. B.
(2001).
Structural Diagnosis of Wiring Networks: Finding Connected Components of Unknown Subgraphs. SIAM Journal on Discrete Mathematics.
14(4), 510-523.
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Shahrokhi, F., & Shi, W.
(2000).
On Crossing Sets, Disjoint Sets, and Pagenumber. Journal of Algorithms in Cognition, Informatics and Logic.
34(1), 40-53.
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Shi, W., Kumar, K., & Lombardi, F.
(2000).
On the complexity of switch programming in fault-tolerant configurable chips. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.
125-133.
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Shi, W., & West, D. B.
(1999).
Diagnosis of Wiring Networks: An Optimal Randomized Algorithm for Finding Connected Components of Unknown Graphs. SIAM Journal on Computing.
28(5), 1541-1551.
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Shi, W., Chang, M., & Fuchs, W. K.
(1996).
Harvest rate of reconfigurable pipelines. IEEE Transactions on Computers.
45(10), 1200-1203.
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Shi, W.
(1996).
A fast algorithm for area minimization of slicing floorplans. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
15(12), 1525-1532.
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Pan, P., Shi, W., & Liu, C. L.
(1996).
Area minimization for hierarchical floorplans. Algorithmica: an international journal in computer science.
15(6), 550-571.
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Shi, W., & Fuchs, W. K.
(1995).
Optimal interconnect diagnosis of wiring networks. IEEE Transactions on Very Large Scale Integration Systems.
3(3), 430-436.
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Pan, P., Shi, W., & Liu, C. L.
(1994).
Area minimization for hierarchical floorplans. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
436-440.
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Zhou, Y., Zhang, Y., Sarin, V., Qiu, W., & Shi, W.
(2016).
Macro Model of Advanced Devices for Parasitic Extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
35(10), 1721-1729.
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conference paper
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Huang, Y., Hu, J., & Shi, W.
(2011).
Lagrangian Relaxation for Gate Implementation Selection. 167-174.
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Li, Z., Papa, D. A., Alpert, C. J., Hu, S., Shi, W., Sze, C., & Zhou, Y.
(2010).
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. 75-82.
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Doddannagari, U., Hu, S., & Shi, W.
(2009).
Fast Characterization of Parameterized Cell Library. 500-505.
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Zhou, Y., Kanj, R., Agarwal, K., Li, Z., Joshi, R., Nassif, S., & Shi, W.
(2009).
The Impact of BEOL Lithography Effects on the SRAM Cell Performance and Yield. Proceedings - International Symposium on Quality Electronic Design, ISQED.
607-+.
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Jiang, Z., & Shi, W.
(2008).
Circuit-wise buffer insertion and gate sizing algorithm with scalability. Design Automation Conference.
708-713.
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Liu, Y., Hu, J., & Shi, W.
(2008).
Multi-Scenario Buffer Insertion in Multi-Core Processor Designs. 15-22.
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Yi, Y., Sarin, V., & Shi, W.
(2008).
An Efficient Inductance Extraction Algorithm for 3-D Interconnects with Frequency Dependent Nonlinear Magnetic Materials. 217-220.
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Yi, Y., Yan, S., Sarin, V., & Shi, W.
(2008).
Development of Fast 3D Parasitic Extraction using Hierarchical Method for Integrated Circuits and Packages. AP-S International Symposium (Digest) (IEEE Antennas and Propagation Society).
13-+.
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Kanj, R., Joshi, R. V., Li, Z., Kuang, J. B., Nqo, H., Zhou, Y., Shi, W., & Nassif, S.
(2008).
SRAM Methodology for Yield and Power Efficiency: Per-Element Selectable Supplies and Memory Reconfiguration Schemes. Proceedings of the International Symposium on Low Power Electronics and Design.
87-92.
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Yi, Y., Li, P., Sarin, V., & Shi, W.
(2007).
Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method. ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS.
7-10.
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Zhou, Y., Li, Z., & Shi, W.
(2007).
Fast capacitance extraction in multilayer, Conformal and embedded dielectric using hybrid boundary element method. Design Automation Conference.
835-+.
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Zhou, Y., Li, Z., Kanj, R. N., Papa, D. A., Nassif, S., & Shi, W.
(2007).
A More Effective $C_{eff}$ for Slew Estimation. 1-4.
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Zhou, Y., Li, Z., Tian, Y., Shi, W., & Liu, F.
(2007).
A new methodology for interconnect parasitics extraction considering photo-lithography effects. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
450-+.
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Jiang, Z., Hu, S., Hu, J., & Shi, W.
(2007).
An efficient alorintham for RLC buffer insertion. Proceedings - International Symposium on Quality Electronic Design, ISQED.
171-+.
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Li, Z., Alpert, C. J., Quay, S. T., Sapatnekar, S., & Shi, W.
(2007).
Probabilistic Congestion Prediction with Partial Blockages. 1-6.
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Waghmode, M., Li, Z., & Shi, W.
(2006).
Buffer insertion in large circuits with constructive solution search techniques. Design Automation Conference.
296-301.
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Jiang, Z., Hu, S., Hu, J., Li, Z., & Shi, W.
(2006).
A New RLC Buffer Insertion Algorithm. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
553-557.
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Yi, Y., Li, P., Sarin, V., & Shi, W.
(2006).
A preconditioned hierarchical algorithm for impedance extraction of interconnects in packages. 99-+.
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Waghmode, M., Gulati, K., Khatri, S. P., & Shi, W.
(2006).
An Efficient, Scalable Hardware Engine for Boolean SATisfiability. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
326-331.
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Li, Z. R., & Shi, W.
(2006).
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
320-325.
-
Hu, S., Alpert, C. J., Hu, J., Karandikar, S., Li, Z., Shi, W., & Sze, C. N.
(2006).
Fast algorithms for slew constrained minimum cost buffering. Design Automation Conference.
308-313.
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Li, P., & Shi, W.
(2006).
Model order reduction of linear networks with massive ports via frequency-dependent port packing. Design Automation Conference.
267-272.
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Li, Z., Sze, C. N., Alpert, C. J., Hu, J., & Shi, W.
(2005).
Making fast buffer insertion even faster via approximation techniques. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
13-18.
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Sze, C. N., Alpert, C. J., Hu, J., & Shi, W. P.
(2005).
Path based buffer insertion. Design Automation Conference.
509-514.
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Li, Z., & Shi, W. P.
(2005).
An O(bn(2)) time algorithm for optimal buffer insertion with b buffer types. Proceedings -Design, Automation and Test in Europe, DATE.
1324-1329.
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Tian, Y., Grimaila, M. R., Shi, W., & Mercer, M. R.
(2005).
An Optimal Test Pattern Selection Method to Improve the Defect Coverage. International Test Conference.
1-9.
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Tian, Y., Shi, W., & Mercer, M. R.
(2005).
Impact of photolithography and mask variability on interconnect parasitics. Proceedings of SPIE.
59920e-59920e-10.
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Wang, J., Yue, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2005).
A Vector-Based Approach for Power Supply Noise Analysis in Test Compaction. International Test Conference.
1-10.
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Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W. P.
(2005).
A circuit level fault model for resistive shorts of MOS gate oxide. Proceedings - International Workshop on Microprocessor Test and Verification.
97-102.
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Wang, J., Lu, X., Qiu, W. Q., Yue, Z. D., Fancler, S., Shi, W. P., & Walker, D.
(2005).
Static compaction of delay tests considering power supply noise. 235-240.
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Qiu, W. Q., Lu, X., Wang, J., Li, Z., Walker, D., & Shi, W. P.
(2004).
A statistical fault coverage metric for realistic path delay faults. 37-42.
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Qiu, W., & Shi, W.
(2004).
Minimum Moment Steiner Trees. 481-488.
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Shi, W. P., Li, Z., & Alpert, C. J.
(2004).
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
609-614.
-
Yan, S., Sarin, V., & Shi, W. P.
(2004).
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics. Design Automation Conference.
788-793.
-
Yu, F., Yao, D., Christensen, D., Neumann, T., Sinner, E., & Knoll, W.
(2004).
Supramolecular interfacial architectures for biosensing. Proceedings of SPIE.
253-266.
-
Qiu, W. Q., Wang, J., Lu, X., Li, Z., Walker, D., & Shi, W. P.
(2004).
At-speed test for path delay faults using practical techniques. 61-66.
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Yan, S., Sarin, V., & Shi, W. P.
(2004).
Fast capacitance extraction using inexact factorization. 285-288.
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Qiu, W. Q., Wang, J., Walker, D., Reddy, D., Lu, X. A., Li, Z., Shi, W. P., & Balachandran, H.
(2004).
K longest paths per gate (KLPG) test generation for scan-based sequential circuits. International Test Conference.
223-231.
-
Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W. P.
(2004).
Longest path selection for delay test under process variation. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
98-103.
-
Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W.
(2004).
PARADE: PARAmetric delay evaluation under process variation. 276-280.
-
Shi, W., & Li, Z.
(2003).
An O(nlogn) time algorithm for optimal buffer insertion. Design Automation Conference.
580-585.
-
Yan, S., Liu, J., & Shi, W.
(2003).
Improving Boundary Element Methods for Parasitic Extraction** This research was supported by NSF grants CCR-0098329, CCR-0113668, EIA-0223785, and ATP grant 512-0266-2001. 261-267.
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Li, Z., Lu, X., & Shi, W. P.
(2003).
Process variation dimension reduction based on SVD. IEEE International Symposium on Circuits and Systems.
672-675.
-
Li, Z., Lu, X., Qiu, W. Q., Shi, W. P., & Walker, D.
(2003).
A circuit level fault model for resistive opens and bridges. 379-384.
-
Qiu, W., Lu, X., Li, Z., Walker, D., & Shi, W.
(2003).
CodSim - A combined delay fault simulator. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
79-88.
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Tian, Y. X., Grimaila, M. R., Shi, W. P., & Mercer, M. R.
(2003).
Minimizing defective part level using a linear programming-based optimal test selection method. Proceedings of the Asian Test Symposium.
354-359.
-
Mahawar, H., Sarin, V., & Shi, W.
(2002).
Fast inductance extraction of large VLSI circuits. 7-pp.
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Mahawar, H., Sarin, V., & Shi, W. P.
(2002).
A solenoidal basis method for efficient inductance extraction. Design Automation Conference.
751-756.
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Shi, W., Liu, J., Kakani, N., & Yu, T.
(1998).
A fast hierarchical algorithm for 3-D capacitance extraction. Design Automation Conference.
212-217.
-
Shahrokhi, F., & Shi, W.
(1996).
Efficient deterministic algorithms for embedding graphs on books. Lecture Notes in Computer Science.
162-168.
-
Shi, W.
(1995).
Optimal algorithm for area minimization of slicing floorplans. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
480-484.
-
Shi, W., & West, D. B.
(1995).
Optimal algorithms for finding connected components of an unknown graph. Lecture Notes in Computer Science.
131-140.
-
Huang, Y., Hu, J., & Shi, W.
(2011).
Lagrangian Relaxation for Gate Implementation Selection. 167-174.
Teaching
teaching activities
- ECEN248 Intro To Dgtl Sym Dsgn Instructor
- ECEN454 Dig Integratedckt Des Instructor
- ECEN485 Directed Studies Instructor
- ECEN491 Research Instructor
- ECEN680 Test&diag Digital Syst Instructor
- ECEN684 Professional Internship Instructor
- ECEN685 Directed Studies Instructor
- ECEN691 Research Instructor
- ECEN714 Digital Integrated Circuit Des Instructor
- ECEN752 Adv In Vlsi Ckt Design Instructor
Works By Students
chaired theses and dissertations
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Bekal, Prasanna (2012-07). Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.
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Chakraborty, Avijit (2015-11). Observability Driven Path Generation for Delay Test.
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Doddannagari, Uday (2009-05). A p-cell approach to integer gate sizing.
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Gupta, Kaustubh (2013-07). Design, Simulation and Modeling of Insulated Gate Bipolar Transistor.
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Huang, Yi-Le (2012-02). An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization.
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Koteeswaran, Prabhavathi (2005-02). Fast dynamic force computation for electrostatic and electromagnetic conductors.
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Li, Zhixing (2014-12). Machine Learning Applied in 2D Parasitic Extraction.
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Li, Zhuo (2006-04). Fast interconnect optimization.
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Lu, Xiang (2006-04). Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits.
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Waghmode, Mandar (2007-04). Buffer insertion in large circuits using look-ahead and back-off techniques.
-
Yan, Shu (2006-04). Efficient numerical methods for capacitance extraction based on boundary element method.
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Yi, Yang (2011-02). Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.
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Yu, Fangqing (2004-09). A divide-and-conquer method for 3D capacitance extraction.
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Zhou, Ying (2010-07). Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.
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Zhuang, Wei (2007-09). A 3-d capacitance extraction algorithm based on kernel independent hierarchical method and geometric moments.
Background
education and training
Contact
first name
- Weiping
has last name
- Shi
mailing address
-
Texas A&M University
Electrical & Computer Engineering
3128 TAMU
College Station, TX 77843-3128
USA
Other
- wshi@tamu.edu