My research interests include computer-aided design of Very Large Scale Integration (VLSI) CAD, including physical design, parasitic extraction, fault diagnosis, variational analysis and process synthesis.
Works By Students
Works By Students
chaired theses and dissertations
Bekal, Prasanna (2012-05).
Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.
Chakraborty, Avijit (2015-12).
Observability Driven Path Generation for Delay Test.
Doddannagari, Uday (2007-12).
A p-cell approach to integer gate sizing.
Gupta, Kaustubh (2013-08).
Design, Simulation and Modeling of Insulated Gate Bipolar Transistor.
Huang, Yi-Le (2010-12).
An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization.
Koteeswaran, Prabhavathi (2004-12).
Fast dynamic force computation for electrostatic and electromagnetic conductors.
Li, Zhixing (2014-12).
Machine Learning Applied in 2D Parasitic Extraction.
Li, Zhuo (2005-12).
Fast interconnect optimization.
Lu, Xiang (2005-12).
Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits.
Waghmode, Mandar (2005-12).
Buffer insertion in large circuits using look-ahead and back-off techniques.
Yan, Shu (2005-12).
Efficient numerical methods for capacitance extraction based on boundary element method.
Yi, Yang (2009-12).
Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.
Yu, Fangqing (2003-05).
A divide-and-conquer method for 3D capacitance extraction.
Zhou, Ying (2010-05).
Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.
Zhuang, Wei (2003-05).
A 3-d capacitance extraction algorithm based on kernel independent hierarchical method and geometric moments.