HR job title
- Professor
- Contact Info
- 1 979 845 3820
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Shi, Weiping Professor
Positions
My research interests include computer-aided design of Very Large Scale Integration (VLSI) CAD, including physical design, parasitic extraction, fault diagnosis, variational analysis and process synthesis.
- Overview
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- Works By Students
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Overview
Publications
selected publications
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academic article
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Zhou, Y., Zhang, Y., Sarin, V., Qiu, W., & Shi, W.
(2016).
Macro Model of Advanced Devices for Parasitic Extraction. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
35(10), 1721-1729.
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Li, Z., Zhou, Y. N., & Shi, W.
(2012).
$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets with $m$ Sinks. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
31(3), 437-441.
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Yi, Y., Wenzel, R., Sarin, V., & Shi, W.
(2009).
Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
28(7), 1106-1110.
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Yi, Y., Wenzel, R., Sarin, V., & Shi, W.
(2009).
Inductance extraction for interconnects in the presence of nonlinear magnetic materials. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
28(1), 1106-1110.
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Liu, Y., Hu, J., & Shi, W.
(2008).
Buffering Interconnect for Multicore Processor Designs. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
27(12), 2183-2196.
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Yi, Y., Li, P., Sarin, V., & Shi, W.
(2008).
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures with Multiple Dielectrics. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
27(11), 1918-1927.
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Gulati, K., Waghmode, M., Khatri, S. P., & Shi, W.
(2008).
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Computers & Digital Techniques.
2(3), 214-229.
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Hu, S., Alpert, C. J., Hu, J., Karandikar, S. K., Li, Z., Shi, W., & Sze, C. N.
(2007).
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
26(11), 2009-2022.
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Sze, C. N., Alpert, C. J., Hu, J., & Shi, W.
(2007).
Path-Based Buffer Insertion. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
26(7), 1346-1355.
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Li, Z., Zhou, Y., & Shi, W.
(2007).
Wire Sizing for Non-Tree Topology. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
26(5), 872-880.
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Yan, S., Sarin, V., & Shi, W.
(2006).
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
25(10), 2282-2286.
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Li, Z., & Shi, W.
(2006).
An $O(Bn^{2})$ Time Algorithm for Optimal Buffer Insertion With $B$ Buffer Types. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
25(3), 484-489.
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Lu, X., Li, Z., Qiu, W., Walker, D., & Shi, W.
(2005).
Longest-Path Selection for Delay Test Under Process Variation. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
24(12), 1924-1929.
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Yan, S., Sarin, V., & Shi, W.
(2005).
Sparse Transformations and Preconditioners for 3-D Capacitance Extraction. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
24(9), 1420-1426.
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Shi, W., & Li, Z.
(2005).
A Fast Algorithm for Optimal Buffer Insertion. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
24(6), 879-891.
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Shi, W., & Su, C.
(2005).
The Rectilinear Steiner Arborescence Problem Is NP-Complete. SIAM Journal on Computing.
35(3), 729-740.
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Shi, W., & Yu, F.
(2004).
A Divide-and-Conquer Algorithm for 3-D Capacitance Extraction. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
23(8), 1157-1163.
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Li, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2003).
A circuit level fault model for resistive bridges. ACM Transactions on Design Automation of Electronic Systems.
8(4), 546-559.
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Shi, W., Liu, J., Kakani, N., & Yu, T.
(2002).
A Fast Hierarchical Algorithm for Three-Dimensional Capacitance Extraction. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
21(3), 330-336.
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Shi, W., & West, D. B.
(2001).
Structural Diagnosis of Wiring Networks: Finding Connected Components of Unknown Subgraphs. FPSAC'10 - 22nd International Conference on Formal Power Series and Algebraic Combinatorics.
14(4), 510-523.
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Shahrokhi, F., & Shi, W.
(2000).
On Crossing Sets, Disjoint Sets, and Pagenumber. Journal of Algorithms.
34(1), 40-53.
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Shi, W., Kumar, K., & Lombardi, F.
(2000).
On the complexity of switch programming in fault-tolerant configurable chips. Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
125-133.
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Shi, W., & West, D. B.
(1999).
Diagnosis of Wiring Networks: An Optimal Randomized Algorithm for Finding Connected Components of Unknown Graphs. SIAM Journal on Computing.
28(5), 1541-1551.
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Pan, P., Shi, W., & Liu, C. L.
(1996).
Area minimization for hierarchical floorplans. Algorithmica.
15(6), 550-571.
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Shi, W.
(1996).
A fast algorithm for area minimization of slicing floorplans. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
15(12), 1525-1532.
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Shi, W., Chang, M., & Fuchs, W. K.
(1996).
Harvest rate of reconfigurable pipelines. IEEE Transactions on Computers.
45(10), 1200-1203.
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Shi, W., & Fuchs, W. K.
(1995).
Optimal interconnect diagnosis of wiring networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
3(3), 430-436.
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Pan, P., Shi, W., & Liu, C. L.
(1994).
Area minimization for hierarchical floorplans. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
436-440.
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Zhou, Y., Zhang, Y., Sarin, V., Qiu, W., & Shi, W.
(2016).
Macro Model of Advanced Devices for Parasitic Extraction. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
35(10), 1721-1729.
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conference paper
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Huang, Y., Hu, J., & Shi, W.
(2011).
Lagrangian relaxation for gate implementation selection. 167-174.
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Li, Z., Papa, D. A., Alpert, C. J., Hu, S., Shi, W., Sze, C., & Zhou, Y.
(2010).
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. 75-82.
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Doddannagari, U., Hu, S., & Shi, W.
(2009).
Fast Characterization of Parameterized Cell Library. 500-505.
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Zhou, Y., Kanj, R., Agarwal, K., Li, Z., Joshi, R., Nassif, S., & Shi, W.
(2009).
The impact of BEOL lithography effects on the SRAM cell performance and yield. 2010 11th International Symposium on Quality Electronic Design (ISQED).
607-612.
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Yi, Y., Sarin, V., & Shi, W.
(2008).
An Efficient Inductance Extraction Algorithm for 3-D Interconnects with Frequency Dependent Nonlinear Magnetic Materials. 217-220.
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Jiang, Z., & Shi, W.
(2008).
Circuit-wise buffer insertion and gate sizing algorithm with scalability. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
708-713.
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Yi, Y., Yan, S., Sarin, V., & Shi, W.
(2008).
Development of Fast 3D Parasitic Extraction using Hierarchical Method for Integrated Circuits and Packages. 2007 IEEE Antennas and Propagation Society International Symposium.
1-4.
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Liu, Y., Hu, J., & Shi, W.
(2008).
Multi-scenario buffer insertion in multi-core processor designs. 15-22.
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Kanj, R., Joshi, R. V., Li, Z., Kuang, J. B., Nqo, H., Zhou, Y., Shi, W., & Nassif, S.
(2008).
SRAM Methodology for Yield and Power Efficiency: Per-Element Selectable Supplies and Memory Reconfiguration Schemes. 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED).
87-92.
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Yi, Y., Li, P., Sarin, V., & Shi, W.
(2007).
Impedance Extraction for 3-D Structures with Multiple Dielectrics Using Preconditioned Boundary Element Method. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
7-10.
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Zhou, Y., Li, Z., Shi, W., & IEEE, ..
(2007).
Fast capacitance extraction in multilayer, Conformal and embedded dielectric using hybrid boundary element method. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
835-+.
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Zhou, Y., Li, Z., Kanj, R. N., Papa, D. A., Nassif, S., & Shi, W.
(2007).
A More Effective $C_{eff}$ for Slew Estimation. 1-4.
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Jiang, Z., Hu, S., Hu, J., & Shi, W.
(2007).
An Efficient Algorithm for RLC Buffer Insertion. 2010 11th International Symposium on Quality Electronic Design (ISQED).
171-175.
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Li, Z., Alpert, C. J., Quay, S. T., Sapatnekar, S., & Shi, W.
(2007).
Probabilistic Congestion Prediction with Partial Blockages. 1-6.
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Zhou, Y., Li, Z., Tian, Y., Shi, W., & Liu, F.
(2007).
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
450-455.
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Jiang, Z., Hu, S., Hu, J., Li, Z., & Shi, W.
(2006).
A New RLC Buffer Insertion Algorithm. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
553-557.
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Yi, Y., Li, P., Sarin, V., & Shi, W.
(2006).
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Interconnects in Packages. 99-102.
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Waghmode, M., Gulati, K., Khatri, S. P., & Shi, W.
(2006).
An Efficient, Scalable Hardware Engine for Boolean SATisfiability. 2005 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS.
326-331.
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Li, Z., & Shi, W.
(2006).
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks. 320-325.
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Waghmode, M., Li, Z., & Shi, W.
(2006).
Buffer insertion in large circuits with constructive solution search techniques. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
296-301.
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Hu, S., Alpert, C. J., Hu, J., Karandikar, S., Li, Z., Shi, W., & Sze, C. N.
(2006).
Fast algorithms for slew constrained minimum cost buffering. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
308-313.
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Li, P., & Shi, W.
(2006).
Model Order Reduction of Linear Networks with Massive Ports via Frequency-Dependent Port Packing. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
267-272.
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Li, Z., Sze, C. N., Alpert, C. J., Hu, J., Shi, W., & IEEE, ..
(2005).
Making fast buffer insertion even faster via approximation techniques. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
13-18.
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Sze, C. N., Alpert, C. J., Hu, J., Shi, W. P., & Soc, I.
(2005).
Path based buffer insertion. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
509-514.
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Tian, Y., Shi, W., & Mercer, M. R.
(2005).
Impact of photolithography and mask variability on interconnect parasitics. 1998 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS.
59920e-59920e-10.
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Wang, J., Yue, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2005).
A Vector-Based Approach for Power Supply Noise Analysis in Test Compaction. IEEE International Test Conference (TC).
1-10.
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Li, Z., & Shi, W.
(2005).
An $O(bn^{2})$ Time Algorithm for Optimal Buffer Insertion with $b$ Buffer Types**This research was supported by the NSF grants CCR-0098329, CCR-0113668, ElA-0223785, ATP grant 512-0266-2001. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1324-1329.
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Tian, Y., Grimaila, M. R., Shi, W., & Mercer, M. R.
(2005).
An Optimal Test Pattern Selection Method to Improve the Defect Coverage. IEEE International Test Conference (TC).
1-9.
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Wang, J., Lu, X., Qiu, W., Yue, Z., Fancler, S., Shi, W., & Walker, D.
(2005).
Static Compaction of Delay Tests Considering Power Supply Noise. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
235-240.
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Yu, F., Yao, D., Christensen, D., Neumann, T., Sinner, E., & Knoll, W.
(2004).
Supramolecular interfacial architectures for biosensing. 1998 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS.
253-266.
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Qiu, W. Q., Lu, X., Wang, J., Li, Z., Walker, D., Shi, W. P., & society, i. C.
(2004).
A statistical fault coverage metric for realistic path delay faults. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
37-42.
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Shi, W., Li, Z., & Alpert, C. J.
(2004).
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. 609-614.
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Qiu, W., & Shi, W.
(2004).
Minimum Moment Steiner Trees. 481-488.
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Lu, X., Li, Z., Shi, W., Qiu, W., & Walker, D.
(2004).
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. 2013 14th International Workshop on Microprocessor Test and Verification.
97-102.
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Qiu, W., Wang, J., Lu, X., Li, Z., Walker, D., & Shi, W.
(2004).
At-Speed Test for Path Delay Faults using Practical Techniques. 61-66.
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Sarin, V., Shi, W., & Yan, S.
(2004).
Fast Capacitance Extraction using Inexact Factorization. 285-288.
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Qiu, W., Wang, J., Walker, D., Reddy, D., Lu, X., Li, Z., Shi, W., & Balachandran, H.
(2004).
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. IEEE International Test Conference (TC).
223-231.
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Lu, X., Li, Z., Qiu, W., Walker, D., & Shi, W.
(2004).
Longest Path Selection for Delay Test Under Process Variation**This research was supported in part by the SRC grant 000-TJ-844, NSF grants CCR-0098329, CCR-0113668, EIA-0223785, and ATP grant 512-0266-2001. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
98-103.
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Lu, X., Li, Z., Qiu, W. Q., Walker, D., Shi, W., SOCIETY, I. C., SOCIETY, I. C., & SOCIETY, I. C.
(2004).
PARADE: PARAmetric delay evaluation under process variation. 276-280.
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Yan, S., Sarin, V., & Shi, W.
(2004).
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
788-793.
-
Shi, W., & Li, Z.
(2003).
An O(nlogn) time algorithm for optimal buffer insertion. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
580-585.
-
Li, Z., Lu, X., Shi, W. P., IEEE, .., & IEEE, ..
(2003).
Process variation dimension reduction based on SVD. 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
672-675.
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Li, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2003).
A Circuit Level Fault Model for Resistive Opens and Bridges. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
379-384.
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Qiu, W., Lu, X., Li, Z., Walker, D., & Shi, W.
(2003).
CodSim - A combined delay fault simulator. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
79-88.
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Yan, S., Liu, J., & Shi, W.
(2003).
Improving Boundary Element Methods for Parasitic Extraction** This research was supported by NSF grants CCR-0098329, CCR-0113668, EIA-0223785, and ATP grant 512-0266-2001. 261-267.
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Tian, Y., Grimaila, M. R., Shi, W., & Mercer, M. R.
(2003).
Minimizing Defective Part Level using a Linear Programming-Based Optimal Test Selection Method. ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS.
354-359.
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Mahawar, H., Sarin, V., & Shi, W.
(2002).
A Solenoidal Basis Method for Efficient Inductance Extraction**This work has been supported in part by National Science Foundation grants NSF-CCR 9984400 and NSF-CCR 0113668 and the Texas Advanced Technology Program grant 000512-0266-2001. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
751-756.
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Mahawar, H., Sarin, V., & Shi, W.
(2002).
Fast inductance extraction of large VLSI circuits. 7-pp.
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Shi, W., Liu, J., Kakani, N., & Yu, T.
(1998).
A fast hierarchical algorithm for 3-D capacitance extraction. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
212-217.
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Shahrokhi, F., & Shi, W.
(1996).
Efficient deterministic algorithms for embedding graphs on books. AD-HOC, MOBILE, AND WIRELESS NETWORKS.
162-168.
-
Shi, W.
(1995).
Optimal algorithm for area minimization of slicing floorplans. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
480-484.
-
Shi, W., & West, D. B.
(1995).
Optimal algorithms for finding connected components of an unknown graph. AD-HOC, MOBILE, AND WIRELESS NETWORKS.
131-140.
-
Huang, Y., Hu, J., & Shi, W.
(2011).
Lagrangian relaxation for gate implementation selection. 167-174.
Teaching
teaching activities
- ECEN248 Intro To Dgtl Sym Dsgn Instructor
- ECEN454 Dig Integratedckt Des Instructor
- ECEN485 Directed Studies Instructor
- ECEN684 Professional Internship Instructor
- ECEN685 Directed Studies Instructor
- ECEN691 Research Instructor
- ECEN714 Digital Integrated Circuit Des Instructor
- ECEN752 Adv In Vlsi Ckt Design Instructor
Works By Students
chaired theses and dissertations
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Bekal, Prasanna (2012-05). Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.
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Chakraborty, Avijit (2015-12). Observability Driven Path Generation for Delay Test.
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Doddannagari, Uday (2007-12). A p-cell approach to integer gate sizing.
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Gupta, Kaustubh (2013-08). Design, Simulation and Modeling of Insulated Gate Bipolar Transistor.
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Huang, Yi-Le (2010-12). An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization.
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Koteeswaran, Prabhavathi (2004-12). Fast dynamic force computation for electrostatic and electromagnetic conductors.
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Li, Zhixing (2014-12). Machine Learning Applied in 2D Parasitic Extraction.
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Li, Zhuo (2005-12). Fast interconnect optimization.
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Lu, Xiang (2005-12). Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits.
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Waghmode, Mandar (2005-12). Buffer insertion in large circuits using look-ahead and back-off techniques.
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Yan, Shu (2005-12). Efficient numerical methods for capacitance extraction based on boundary element method.
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Yi, Yang (2009-12). Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.
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Yu, Fangqing (2003-05). A divide-and-conquer method for 3D capacitance extraction.
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Zhou, Ying (2010-05). Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.
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Zhuang, Wei (2003-05). A 3-d capacitance extraction algorithm based on kernel independent hierarchical method and geometric moments.
Background
education and training
Contact
first name
- Weiping
has last name
- Shi
mailing address
-
Texas A&M University
Electrical & Computer Engineering
3128 TAMU
College Station, TX 77843-3128
USA
Other
- wshi@tamu.edu