My research interests include computer-aided design of Very Large Scale Integration (VLSI) CAD, including physical design, parasitic extraction, fault diagnosis, variational analysis and process synthesis.
Hu, S., Alpert, C. J., Hu, J., Karandikar, S. K., Li, Z., Shi, W., & Sze, C. N.
(2007).Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
26(11), 2009-2022.
Sze, C. N., Alpert, C. J., Hu, J., & Shi, W.
(2007).Path-Based Buffer Insertion. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
26(7), 1346-1355.
Li, Z., Zhou, Y., & Shi, W.
(2007).Wire Sizing for Non-Tree Topology. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
26(5), 872-880.
Kanj, R., Joshi, R., Li, Z., Kuang, J. B., Ngo, H., Zhou, Y., Shi, W., & Nassif, S.
(2008).SRAM methodology for yield and power efficiency. 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED).
87-92.
Sze, C. N., Alpert, C. J., Hu, J., Shi, W. P., & Soc, I.
(2005).Path based buffer insertion. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
509-514.
Qiu, W., Lu, X., Li, Z., Walker, D., & Shi, W.
(2003).CodSim - A combined delay fault simulator. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
79-88.