A circuit level fault model for resistive shorts of MOS gate oxide
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Previous researchers in logic testing focused on shorts in MOS gate oxides that have zero-resistance. However, most shorts are resistive and may cause delay faults. In this paper, we propose a simple and realistic delay fault model for gate oxide shorts. A reasonably accurate method is proposed to compute delay change due to resistive shorts. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. 2005 IEEE.
name of conference
5th International Workshop on Microprocessor Test and Verification. Common Challenges and Solutions
Fifth International Workshop on Microprocessor Test and Verification (MTV'04)
author list (cited authors)
Xiang Lu, .., Zhuo Li, .., Wangqi Qiu, .., Walker, D., & Weiping Shi.
complete list of authors