With the scale of interconnect number grows to billions, parasitic capacitance extraction speed is an important issue for fast turn-around time for designers. In this thesis, we propose to build a regression model for the input interconnect geometry to predict the parasitic capacitance based on machine learning. A simplification algorithm is proposed to reduce the number of conductors for quicker and easier regression modeling and the regression models can improve by machine learning technique. Experimental results show that the proposed method is significantly faster than existing method and provides satisfactory accuracy.
With the scale of interconnect number grows to billions, parasitic capacitance extraction speed is an important issue for fast turn-around time for designers.
In this thesis, we propose to build a regression model for the input interconnect geometry to predict the parasitic capacitance based on machine learning. A simplification algorithm is proposed to reduce the number of conductors for quicker and easier regression modeling and the regression models can improve by machine learning technique.
Experimental results show that the proposed method is significantly faster than existing method and provides satisfactory accuracy.
