At-speed test for path delay faults using practical techniques Conference Paper

abstract

• To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Most existing test generation tools are either inefficient in automatically identifying the longest testable paths due to the high computational complexity or do not support at-speed test using existing practical design-for-testability structures, such as scan design. In this work a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The two strategies are compared and the test generation efficiency is evaluated on the ISCAS89 benchmark circuits. 2004 IEEE.

name of conference

• Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)

authors

• Shi, Weiping
• Walker, Duncan

published proceedings

• DBT 2004: PROCEEDINGS OF THE 2004 IEEE INTERNATIONAL WORKSHOP ON CURRENT & DEFECT BASED TESTING

author list (cited authors)

• Qiu, W. Q., Wang, J., Lu, X., Li, Z., Walker, D., & Shi, W. P.

citation count

• 3

complete list of authors

• Qiu, WQ||Wang, J||Lu, X||Li, Z||Walker, DMH||Shi, WP

publication date

• January 2004

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• 40 Engineering
• 4008 Electrical Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/DBT.2004.1408957

International Standard Book Number (ISBN) 10

• 0-7803-8950-6

International Standard Book Number (ISBN) 13

• 9780780389502

start page

• 61

end page

• 66

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fdbt.2004.1408957