A circuit level fault model for resistive opens and bridges Conference Paper uri icon


  • 2003 IEEE. Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.

name of conference

  • Proceedings. 21st VLSI Test Symposium, 2003.

published proceedings


author list (cited authors)

  • Li, Z., Lu, X., Qiu, W. Q., Shi, W. P., & Walker, D.

citation count

  • 36

complete list of authors

  • Li, Z||Lu, X||Qiu, WQ||Shi, WP||Walker, DMH

publication date

  • January 2003