Buffer insertion in large circuits with constructive solution search techniques Conference Paper uri icon

abstract

  • Most existing buffer insertion algorithms, such as van Gin-neken's algorithm, consider only individual nets. As a result, these algorithms tend to over buffer when applied to com-binational circuits, since it is difficult to decide how many buffers to insert in each net. Recently, Sze, et al. [1] pro-posed a path-based algorithm for buffer insertion in combi-national circuits. However their algorithm is inefficient for large circuits when there are many critical paths. In this paper, we present a new buffer insertion algorithm for combinational circuits such that the timing requirements are met and the buffer cost is minimized. Our algorithm it-eratively inserts buffers in the circuit to improve the circuit delay. The core of this algorithm is simple but effective tech-nique that guides the search for a good buffering solution. Experimental results on ISCAS85 circuits show that our new algorithm on average uses 36% less buffers and runs 3 times faster than Sze's algorithm. Copyright 2006 ACM.

name of conference

  • Proceedings of the 43rd annual conference on Design automation - DAC '06

published proceedings

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

author list (cited authors)

  • Waghmode, M., Li, Z., & Shi, W.

citation count

  • 9

complete list of authors

  • Waghmode, M||Li, Zhuo||Shi, Weiping

publication date

  • July 2006