publication venue for
- Congestion-Driven Codesign of Power and Signal Networks **This work was supported in part by the NSF under award CCR-0098117 and by the SRC under contract 99-TJ-714.. 64-69. 2002
- A practical methodology for early buffer and wire resource allocation. 189-194. 2001
- FAR-DS: Full-plane AWE Routing with Driver Sizing. 84-89. 1999
- Novel VLSI layout fabric for deep sub-micron applications. 491-496. 1999
- Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs 2020
- A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation 2019
- Enabling High-Dimensional Bayesian Optimization for Efficient Failure Detection of Analog and Mixed-Signal Circuits 2019
- Optimal design of JPEG hardware under the approximate computing paradigm 2016
- The Cat and Mouse in Split Manufacturing 2016
- A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms 2015
- Bandwidth-efficient on-chip interconnect designs for GPGPUs 2015
- Joint precision optimization and high level synthesis for approximate computing 2015
- Detecting malicious modifications of data in third-party intellectual property cores 2015
- Vortex 2015
- A red team/blue team assessment of functional analysis methods for malicious circuit identification 2014
- Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine 2013
- Dynamic voltage and frequency scaling for shared resources in multicore processor designs 2013
- Application of logic synthesis to the understanding and cure of genetic diseases 2012
- Boolean satisfiability using noise based logic 2012
- Boolean Satisfiability using Noise Based Logic 2012
- Security analysis of logic obfuscation 2012
- Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system 2011
- Detecting tangled logic structures in VLSI netlists 2010
- Reliability aware power management for dual-processor real-time embedded systems 2010
- Separatrices in high-dimensional state space: System-theoretical tangent computation and application to SRAM dynamic stability analysis 2010
- GPU-based parallelization for fast circuit optimization 2009
- Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems 2009
- A fast, analytical estimator for the SEU-induced pulse width in combinational designs 2008
- Circuit-wise buffer insertion and gate sizing algorithm with scalability 2008
- Feed back-control led reliability-aware power management for real-time embedded systems 2008
- Forbidden transition free crosstalk avoidance CODEC design 2008
- IntellBatt: Towards smarter battery design 2008
- Predictive Dynamic Thermal Management for multicore systems 2008
- Towards acceleration of fault simulation using Graphics Processing Units 2008
- A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip 2007
- Fast capacitance extraction in multilayer, Conformal and embedded dielectric using hybrid boundary element method 2007
- Gate sizing for cell library-based designs 2007
- A design approach for radiation-hard digital electronics 2006
- A PLA based Asynchronous Micropipelining Approach for Subthreshold Circuit Design 2006
- A PLA based asynchronous micropipelining approach for subthreshold circuit design 2006
- A design approach for radiation-hard digital electronics 2006
- Buffer insertion in large circuits with constructive solution search techniques 2006
- Fast algorithms for slew constrained minimum cost buffering 2006
- Model Order Reduction of Linear Networks with Massive Ports via Frequency-Dependent Port Packing 2006
- Standard cell characterization considering lithography induced variations 2006
- Steiner network construction for timing critical nets 2006
- A Variation-tolerant sub-threshold design approach 2005
- Navigating registers in placement for clock network minimization 2005
- Path based buffer insertion 2005
- A Self-adjusting Scheme to Determine the Optimum RBB by Monitoring Leakage Currents 2005
- TCAM enabled on-chip logic minimization 2005
- A robust algorithm for approximate Compatible Observability Don't Care (CODC) computation 2004
- Fast and flexible buffer trees that navigate the physical layout environment 2004
- Requirement-based design methods for adaptive communications links 2004
- Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics 2004
- Energy characterization of filesystems for diskless embedded systems 2004
- Reducing clock skew variability via cross links 2004
- An O(nlogn) time algorithm for optimal buffer insertion 2003
- Global resource sharing for synthesis of control data flow graphs on FPGAs 2003
- A solenoidal basis method for efficient inductance extraction 2002
- 'Timing Closure by Design,' a high frequency microprocessor design methodology 2000
- A fast hierarchical algorithm for 3-D capacitance extraction 1998
- Engineering change in a non-deterministic FSM setting 1996