TCAM enabled on-chip logic minimization Conference Paper uri icon


  • This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory efficient implementation suitable for emerging on-chip minimization applications. The paper presents a detailed design of the on-chip minimizer and shows that it requires very little hardware resources to achieve acceptable quality of minimization. An incremental insertion and bulk deletion is achieved in 0.25 s and 3.8 ms respectively and a compaction of 100000 entries in 25 ms using just 300 TCAM entries. Copyright 2005 ACM.

name of conference

  • Proceedings of the 42nd annual conference on Design automation - DAC '05

published proceedings


author list (cited authors)

  • Ahmad, S., & Mahapatra, R.

citation count

  • 1

complete list of authors

  • Ahmad, S||Mahapatra, R

publication date

  • January 2005